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零件编号 | QL2009-2PQ208C | ||
描述 | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility | ||
制造商 | ETC | ||
LOGO | |||
1 Page
QL2009
3.3V and 5.0V pASIC® 2 FPGA
Combining Speed, Density, Low Cost and Flexibility
Rev. C
pASIC 2
HIGHLIGHTS
… 9,000
usable ASIC gates,
225 I/O pins
QL2009
Block Diagram
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency and performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
-16-bit counter speeds exceeding 200 MHz
-9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os
-3-layer metal ViaLink® process for small die sizes
-100% routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
3
672
Logic
Cells
3-35
QL2009
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ……………….. -0.5 to 7.0V
Input Voltage ……….… -0.5 to VCC +0.5V
ESD Pad Protection ….…………… ±2000V
DC Input Current ….……………… ±20 mA
Latch-up Immunity ………………. ±200 mA
Storage Temperature……..…….. -65°C to + 150°C
Lead Temperature ………….………………. 300°C
5 Volt OPERATING RANGE
Symbol
Parameter
VCC
TA
TC
K
Supply Voltage
Ambient Temperature
Case Temperature
-X Speed Grade
Delay Factor -0 Speed Grade
-1 Speed Grade
-2 Speed Grade
Industrial
Min Max
4.5 5.5
-40 85
0.4 2.75
0.4 2.00
0.4 1.61
0.4 1.35
Commercial
Min Max
4.75 5.25
0 70
0.46
0.46
0.46
0.46
2.55
1.85
1.50
1.25
Unit
V
°C
°C
DC CHARACTERISTICS over 5V operating range
Symbol
VIH
VIL
Parameter
Input HIGH Voltage
Input LOW Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
II Input Leakage Current
IOZ 3-State Output Leakage Current
CI Input Capacitance [2]
IOS Output Short Circuit Current [3]
ICC D.C. Supply Current [4]
Conditions
IOH = -4 mA
IOH = -24 mA/-16 mA [1]
IOH = -10 µA
IOL = 24 mA/16 mA [1]
IOL = 10 µA
VI = VCC or GND
VI = VCC or GND
VO = GND
VO = VCC
VI, VIO = VCC or GND
Min
2.0
3.7
2.4
VCC-0.1
-10
-10
-15
40
2 (typ)
Max
0.8
0.45
0.1
10
10
10
-120
210
10
Unit
V
V
V
V
V
V
V
µA
µA
pF
mA
mA
mA
Notes:
[1] -24 mA IOH and 24 mA IOL apply only to -1/-2 commercial grade devices. These speed grades are
also PCI-compliant. All other devices have -16 mA IOH and 16 mA IOL specifications.
[2] Capacitance is sample tested only.
[3] Only one output at a time. Duration should not exceed 30 seconds.
[4] For -0/-1/-2 commercial grade devices only. Maximum ICC is 20 mA for -X commercial grade
devices and 15mA for all industrial grade devices. For AC conditions, contact QuickLogic customer
engineering.
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页数 | 12 页 | ||
下载 | [ QL2009-2PQ208C.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
QL2009-2PQ208C | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility | ETC |
QL2009-2PQ208I | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility | ETC |
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