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PDF ( 数据手册 , 数据表 ) P90CL301BFH

零件编号 P90CL301BFH
描述 Low voltage 16-bit microcontroller
制造商 NXP Semiconductors
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P90CL301BFH 数据手册, 描述, 功能
INTEGRATED CIRCUITS
DATA SHEET
P90CL301BFH (C100)
Low voltage 16-bit microcontroller
Preliminary specification
File under Integrated Circuits, IC17
1996 Dec 11







P90CL301BFH pdf, 数据表
Philips Semiconductors
Low voltage 16-bit microcontroller
Preliminary specification
P90CL301BFH (C100)
6 SYSTEM CONTROL
6.1 Memory organization
The maximum external address space of the controller is
16 Mbytes. It can be partitioned into five address spaces.
These address spaces are designated as either User or
Supervisor space and as either Program or Data space or
as interrupt acknowledge.
For slow memories the CPU can be programmed to insert
a number of wait states. This is done via the eight
Chip-select Control Registers CS0N to CS7N; further to
be denoted as CSnN, where n = 0 to 7. The number of
inserted wait states can vary from 0 to 6, or wait states are
inserted until the DTACK is pulled LOW by the external
address decoding circuitry. If DTACK is asserted
continuously, the P90CL301BFH will run without wait
states using bus cycles of three or four clock periods
depending on the state of the FBC bit in the SYSCON
register.
6.1.1 MEMORY MAP
The memory address space is divided as shown in
Table 2; short addressing space with A31 to A15 = 1.
Table 2 Memory address space
ADDRESS (HEX)
DESCRIPTION
0000 0000 to 00FF FFFF external 16 Mbytes
memory
0100 0000 to 8000 FFFF not used
8001 0000 to 8001 FFFF off-chip 64 kbytes on 8051
bus
8002 0000 to FFFF 7FFF not used
FFFF 8000 to FFFF 8AFF internal registers
FFFF 8B00 to FFFF 8FFF not used
FFFF 9000 to FFFF 91FF internal 512 bytes RAM
FFFF 9200 to FFFF BFFF not used
FFFF C000 to FFFF C0FF internal 256 bytes
Test-ROM
FFFF C100 to FFFF FFFF not used
6.2 Programmable chip-select
In order to reduce the external components associated
with memory interface, the P90CL301BFH provides
8 programmable chip-selects. A specific chip-select CSBT
provides default reset values to support a bootstrap
operation.
Each chip-select can be programmed with:
A base address (A23 to A19)
A memory bank width of 512 kbytes, 1, 2, 4 or 8 Mbytes
memory size
A number of wait states (0 to 6 states, or wait for
DTACK) to adapt the bus cycle to the memory cycle
time.
Chip-selects can be synchronized with read, write, or both
read and write, either Address strobe or Data strobe. They
can also be programmed to address low byte, high byte or
word.
Each chip-select is controlled by a control register CSnN
(n = 0 to 7). The control registers are described in
Table 3 to 7.
The RESET instruction does not affect the contents of the
CSnN registers.
Register CS7N corresponds to register CSBT (address
FFFF 8A0EH). After reset CSBT is programmed with a
block size of 8 Mbytes with:
A19 to A23 at logic 0
M19 to M22 at logic 1
6 wait states
read only mode.
The other chip-selects are held HIGH and will be activated
after initialization of their control registers.
When programmed in reduced access mode (read only,
write only, low byte, high byte), the wait states are
generated internally and if there is any access-violation
when the bit WD in the SYSCON register is set to a logic 1
(time-out), the processor will execute a bus error after the
time-out delay.
1996 Dec 11
8







P90CL301BFH equivalent, schematic
Philips Semiconductors
Low voltage 16-bit microcontroller
Preliminary specification
P90CL301BFH (C100)
6.7 Interrupt controller
An interrupt controller handles all internal and external
interrupts. It delivers the interrupt with the highest priority
level to the CPU. The following interrupt requests are
generated by the on-chip peripherals:
I2C-bus
UARTs: received data / transmitted data
Timers: two flags for the timers T0 and T1
ADC: analog-to-digital conversion completed.
The external interrupt requests are generated with the pins
NMIN and the seven external interrupts INT0 to INT6.
6.7.1 INTERRUPT ARBITRATION
The interrupt priority levels are programmable with a value
between 0 and 7. Level 7 has the highest priority, level 0
disables the corresponding interrupt source. In case of
interrupt requests of equal priority level at the same time a
hardware priority mechanism gives priority order as shown
in Table 16.
The execution of interrupt routines can be interrupted by
another interrupt request of a higher priority level. In 68070
mode (SYSCON bit IM = 1) when an interrupt is serviced
by the CPU, the corresponding level is loaded into the
Status Register. This prevents the current interrupt from
getting interrupted by any other interrupt request on the
same or a lower priority level. If IM is reset, priority level 7
will always be loaded into the Status Register and so the
current interrupt cannot be interrupted by an interrupt
request of a level less than 7.
Each on-chip peripheral unit including the eight interrupt
lines generate only auto-vectored interrupts. No
acknowledge is necessary. For external interrupts the
vectors 25 to 31 are used, for on-chip peripheral circuits a
second table of 7 vectors are used (57 to 63); see
Section 7.3.2.
Table 16 Priority order
SIGNAL
NMIN
INT6
INT5
INT4
INT3
INT2
INT1
INT0
I2C-bus
ADC
UART1 receiver
UART1 transmitter
UART0 receiver
UART0 transmitter
Timer 1
Timer 0
PRIORITY ORDER
highest
lowest
6.7.2 EXTERNAL LATCHED INTERRUPTS
NMIN and INT0 to INT6 are 8 external interrupt inputs.
These pins are connected to the interrupt function only
when the corresponding bit in the SPCON control register
is set (see Section 8.2; Table 29). Seven interrupt inputs
INT0 to INT6 are edge sensitive on HIGH-to-LOW
transition and their priority levels are programmable.
The interrupt NMIN is non-maskable (except if it is
programmed as a port) and is also edge sensitive on
HIGH-to-LOW transition. The priority level of NMIN is fixed
to 7.
The external interrupts are controlled by the registers
LIR0 to LIR3; see Tables 17 and 18.
6.7.2.1 Latched Interrupt Registers (LIR0 to LIR3)
Table 17 Latched Interrupt Registers
ADDRESS REGISTER
FFF 8101H LIR0
FFF 8103H LIR1
FFF 8105H LIR2
FFF 8107H LIR3
7
PIR1
PIR3
PIR5
PIR7
6
IPL1.2
IPL3.2
IPL5.2
1
5
IPL1.1
IPL3.1
IPL5.1
1
4
IPL1.0
IPL3.0
IPL5.0
1
3
PIR0
PIR2
PIR4
PIR6
2
IPL0.2
IPL2.2
IPL4.2
IPL6.2
1
IPL0.1
IPL2.1
IPL4.1
IPL6.1
0
IPL0.0
IPL2.0
IPL4.0
IPL6.0
1996 Dec 11
16










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