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PDF ( 数据手册 , 数据表 ) SMP04EP

零件编号 SMP04EP
描述 CMOS Quad Sample-and-Hold Amplifier
制造商 Analog Devices
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SMP04EP 数据手册, 描述, 功能
a
FEATURES
Four Independent Sample-and-Holds
Internal Hold Capacitors
High Accuracy: 12 Bit
Very Low Droop Rate: 2 mV/s typ
Output Buffers Stable for CL 500 pF
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Applications
Monolithic Low Power CMOS Design
APPLICATIONS
Signal Processing Systems
Multichannel Data Acquisition Systems
Automatic Test Equipment
Medical and Analytical Instrumentation
Event Analysis
DAC Deglitching
CMOS Quad
Sample-and-Hold Amplifier
SMP04*
FUNCTIONAL BLOCK DIAGRAM
VDD
SMP04
VIN1
S/H1
VIN2
S/H2
VIN3
S/H3
VIN4
S/H4
VSS
VSS
VSS
VSS
VOUT1
VOUT2
VOUT3
VOUT4
DGND
VSS
GENERAL DESCRIPTION
The SMP04 is a monolithic quad sample-and-hold; it has four
internal precision buffer amplifiers and internal hold capacitors.
It is manufactured in ADI’s advanced oxide isolated CMOS
technology to obtain the high accuracy, low droop rate and fast
acquisition time required by data acquisition and signal process-
ing systems. The device can acquire an 8-bit input signal to
± 1/2 LSB in less than four microseconds. The SMP04 can
operate from single or dual power supplies with TTL/CMOS
logic compatibility. Its output swing includes the negative supply.
The SMP04 is ideally suited for a wide variety of sample-and-
hold applications, including amplifier offset or VCA gain adjust-
ments. One or more can be used with single or multiple DACs
to provide multiple setpoints within a system.
The SMP04 offers significant cost and size reduction over
equivalent module or discrete designs. It is available in a
16-lead hermetic or plastic DIP and surface mount SOIC
packages. It is specified over the extended industrial tem-
perature range of –40°C to +85°C.
*Protected by U.S. Patent No. 4,739,281.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998







SMP04EP pdf, 数据表
SMP04
FREQUENCY DOMAIN PERFORMANCE
The SMP04 has been characterized in the frequency domain for
those applications that require capture of dynamic signals. See
Figure 16a for typical 86.1 kHz sample rate and an 8 kHz input
signal. Typically, the SMP04 can sample at rates up to 85 kHz.
In addition to the maximum sample rate, a minimum sample
pulsewidth will also be acceptable for a given design. Our testing
shows a drop in performance as the sample pulsewidth becomes
less than 4 µs.
10 dB/DIV RANGE 15.0 dBm 6.0 dBm
START 1 000.0 Hz
STOP 100 000.0 Hz
a.
10 dB/DIV RANGE 15.0 dBm 6.3 dBm
START 1 000.0 Hz
STOP 100 000.0 Hz
b.
Figure 16. Spectral Response at a Sampling Frequency of
86 kHz. Photo (a) Shows a 20 kHz Carrier Frequency and
Photo (b) Shows an 8 kHz Frequency.
Optimizing Dynamic Performance of the SMP04
Various operating parameters such as input voltage amplitude,
sampling pulsewidth and, as mentioned before, supply bypass-
ing and grounding all have an effect on the signal-to-noise ratio.
Table I shows the SNR versus input level for the SMP04.
Distortion of the SMP04 is reduced by increasing the supply
voltage. This has the effect of increasing the positive slew rate.
Table II shows data taken at 12.3 kHz sample rate and 2 kHz
input frequency. Total harmonic distortion is dominated by the
second and third harmonics.
Table III shows the effect of sampling pulsewidth on the SNR of
the SMP04. The recommended operating pulsewidth should be
a minimum of 5 µs to achieve a good balance between acqui-
sition time and SNR for the 1.4 V p-p signal shown. For larger
swings the pulsewidth will need to be larger to account for
the time required for the signal to slew the additional voltage.
This could be used as a method of measuring acquisition
time indirectly.
Table I. SNR vs. VIN
Input
Voltage
(V p-p)
SNR
(dB)
1 –61
2 –53
3 –50
4 –47
5 –45
6 –44
Conditions: VS = ± 6 V, fS = 14.4 kHz,
fIN = 1.8 kHz, tPW = 10 µs.
Table II. SNR vs. Supply Voltage
Supply
Voltage
(V)
10
12
14
15
16
17
2nd
(dB)
–49
–55
–60
–62
–63
–65
3rd
(dB)
–62
–71
–80
<–80
<–83
<–85
Table III. SNR vs. Sample Pulsewidth
Sample
Pulsewidth
(s)
1
2
3
4
5
6
7
SNR
(dB)
–37
–44
–50
–54
–54.9
–55
–55.3
Conditions: VS = ± 6 V, VIN = 1.4 V p-p,
fS = 14.4 kHz, fIN = 1.8 kHz.
–8– REV. D














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