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PDF ( 数据手册 , 数据表 ) TE28F016B3T150

零件编号 TE28F016B3T150
描述 SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE
制造商 Intel Corporation
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TE28F016B3T150 数据手册, 描述, 功能
E
PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK
BYTE-WIDE
8-MBIT (1024K x 8), 16-MBIT (2056K x 8)
FLASH MEMORY FAMILY
28F008B3, 28F016B3
n Flexible SmartVoltage Technology
2.7V–3.6V Program/Erase
2.7V–3.6V Read Operation
12V VPP Fast Production
Programming
n 2.7V or 1.8V I/O Option
Reduces Overall System Power
n Optimized Block Sizes
Eight 8-Kbyte Blocks for Data,
Top or Bottom Locations
Up to Thirty-One 64-Kbyte Blocks
for Code
n High Performance
2.7V–3.6V: 120 ns Max Access Time
n Block Locking
VCC-Level Control through WP#
n Low Power Consumption
20 mA Maximum Read Current
n Absolute Hardware-Protection
VPP = GND Option
VCC Lockout Voltage
n Extended Temperature Operation
–40°C to +85°C
n Supports Code plus Data Storage
Optimized for FDI, Flash Data
Integrator Software
Fast Program Suspend Capability
Fast Erase Suspend Capability
n Extended Cycling Capability
10,000 Block Erase Cycles
n Automated Byte Program and Block
Erase
Command User Interface
Status Registers
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
n Reset/Deep Power-Down
1 µA ICCTypical
Spurious Write Lockout
n Standard Surface Mount Packaging
48-Ball µBGA* Package
40-Lead TSOP Package
n Footprint Upgradeable
Upgradeable from 2-, 4- and 8-Mbit
Boot Block
n ETOX™ V (0.4 µ) Flash Technology
n x8-Only Input/Output Architecture
For Space-Constrained 8-bit
Applications
The new Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.4µ technology, represents a feature-
rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I/O at 1.8V, which significantly reduces system active power and
interfaces to 1.8V controllers. A new blocking scheme enables code and data storage within a single device.
Add to this the Intel-developed Flash Data Integrator (FDI) software and you have the most cost-effective,
monolithic code plus data storage solution on the market today. Smart 3 Advanced Boot Block Byte-Wide
products will be available in 40-lead TSOP and 48-ball µBGA* packages. Additional information on this
product family can be obtained by accessing Intel’s WWW page: http://www.intel.com/design/flcomp
May 1997
Order Number: 290605-001







TE28F016B3T150 pdf, 数据表
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
E
1 2 34
56
7
8
A A14 A12
A8 VPP WP# NC A7
A4
B A15
A10
WE#
RP#
A19
A18
A5
A2
C A16 A13
A9
A6 A3 A1
D
A17
NC
D5
NC
D2
NC CE#
A0
E VCCQ
A11
D6
NC
D3
NC
D0 GND
F
GND
D7
NC
D4
VCC NC
D1 OE#
0605-03
NOTE:
Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.
Routing is not recommended in this area.
Figure 2. 8-Mbit 48-Ball µBGA* Chip Size Package
8 PRELIMINARY







TE28F016B3T150 equivalent, schematic
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
E
reached using the commands summarized in Table
4. A comprehensive chart showing the state
transitions is in Appendix B.
3.2.1
READ ARRAY
When RP# transitions from VIL (reset) to VIH, the
device will be in the read array mode and will
respond to the read control inputs (CE#, address
inputs, and OE#) without any commands being
written to the CUI.
When the device is in the read array mode, four
control signals must be controlled to obtain data at
the outputs.
WE# must be logic high (VIH)
CE# must be logic low (VIL)
OE# must be logic low (VIL)
RP# must be logic high (VIH)
In addition, the address of the desired location must
be applied to the address pins.
If the device is not in read array mode, as would be
the case after a program or erase operation, the
Read Array command (FFH) must be written to the
CUI before array reads can take place.
Table 4. Command Codes and Descriptions
Code Device Mode
Description
00
Invalid/
Unassigned commands that should not be used. Intel reserves the right to
Reserved redefine these codes for future functions.
FF Read Array Places the device in read array mode, such that array data will be output on the
data pins.
40
Program
This is a two-cycle command. The first cycle prepares the CUI for a program
Set-Up
operation. The second cycle latches addresses and data information and
initiates the WSM to execute the Program algorithm. The flash outputs status
register data when CE# or OE# is toggled. A Read Array command is required
after programming to read array data. See Section 3.2.4.
10
Alternate
(See 40H/Program Set-Up)
Program Set-Up
20
Erase
Prepares the CUI for the Erase Confirm command. If the next command is not
Set-Up
an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the
status register to a “1,” (b) place the device into the read status register mode,
and (c) wait for another command. See Section 3.2.5.
D0
Program
If the previous command was an Erase Set-Up command, then the CUI will
Resume
close the address and data latches, and begin erasing the block indicated on the
address pins. If a program or erase operation was previously suspended, this
Erase Resume/ command will resume that operation.
Erase Confirm
During program/erase, the device will respond only to the Read Status Register,
Program Suspend/Erase Suspend commands and will output status register
data when CE# or OE# is toggled.
16 PRELIMINARY










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