DataSheet8.cn


PDF ( 数据手册 , 数据表 ) TE28F010-150

零件编号 TE28F010-150
描述 28F010 1024K (128K X 8) CMOS FLASH MEMORY
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


1 Page

No Preview Available !

TE28F010-150 数据手册, 描述, 功能
E
28F010 1024K (128K X 8) CMOS
FLASH MEMORY
8
n Flash Electrical Chip-Erase
1 Second Typical Chip-Erase
n Quick-Pulse Programming Algorithm
10 µs Typical Byte-Program
2 Second Chip-Program
n 100,000 Erase/Program Cycles
n 12.0 V ±5% VPP
n High-Performance Read
90 ns Maximum Access Time
n CMOS Low Power Consumption
10 mA Typical Active Current
50 µA Typical Standby Current
0 Watts Data Retention Power
n Integrated Program/Erase Stop Timer
n Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
n Noise Immunity Features
±10% VCC Tolerance
Maximum Latch-Up Immunity
through EPI Processing
n ETOX™ Nonvolatile Flash Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
n JEDEC-Standard Pinouts
32-Pin Plastic Dip
32-Lead PLCC
32-Lead TSOP
(See Packaging Spec., Order #231369)
n Extended Temperature Options
Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on-
board during subassembly test; in-system during final test; and in-system after sale. The 28F010 increases
memory flexibility, while contributing to time and cost savings.
The 28F010 is a 1024 kilobit nonvolatile memory organized as 131,072 bytes of eight bits. Intel’s 28F010 is
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel's ETOX™ (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0 V VPP supply, the
28F010 performs 100,000 erase and program cycles—well within the time limits of the quick-pulse
programming and quick-erase algorithms.
Intel's 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds,
low power consumption, and immunity to noise. Its 90 ns access time provides zero wait-state performance
for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 µA translates into
power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved
through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on
address and data pins, from –1 V to VCC + 1 V.
With Intel's ETOX process technology base, the 28F010 builds on years of EPROM experience to yield the
highest levels of quality, reliability, and cost-effectiveness.
December 1997
Order Number: 290207-012







TE28F010-150 pdf, 数据表
E
28F010
290207-4
Figure 3. 28F010 in a 80C186 System
2.0 PRINCIPLES OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F010 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power
supplies during erasure and programming; and
maximum EPROM compatibility.
In the absence of high voltage on the VPP pin, the
28F010 is a read-only memory. Manipulation of the
external memory control pins yields the standard
EPROM read, standby, output disable, and
intelligent identifier operations.
The same EPROM read, standby, and output
disable operations are available when high voltage
is applied to the VPP pin. In addition, high voltage
on VPP enables erasure and programming of the
device. All functions associated with altering
memory contents—intelligent identifier, erase,
erase verify, program, and program verify—are
accessed via the command register.
8
Commands are written to the register using
standard microprocessor write timings. Register
contents serve as input to an internal state machine
which controls the erase and programming circuitry.
Write cycles also internally latch addresses and
data needed for programming or erase operations.
With the appropriate command written to the
register, standard microprocessor read timings
output array data, access the intelligent identifier
codes, or output data for erase and program
verification.
2.1 Integrated Stop Timer
Successive command write cycles define the
durations of program and erase operations;
specifically, the program or erase time durations are
normally terminated by associated Program or
Erase Verify commands. An integrated stop timer
provides simplified timing control over these
operations; thus eliminating the need for maximum
program/erase timing specifications. Programming
and erase pulse durations are minimums only.
When the stop timer terminates a program or erase
operation, the device enters an inactive state and
remains inactive until receiving the appropriate
Verify or Reset command.







TE28F010-150 equivalent, schematic
E
28F010
3.0 DESIGN CONSIDERATIONS
3.1 Two-Line Output Control
Flash memories are often used in larger memory
arrays. Intel provides two read control inputs to
accommodate multiple memory connections. Two-
line control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an
address decoder output should drive chip-enable,
while the system’s read signal controls all flash
memories and other parallel memories. This
assures that only enabled memory devices have
active outputs, while deselected devices maintain
the low power standby condition.
3.2 Power Supply Decoupling
Flash memory power-switching characteristics
require careful device decoupling. System
designers are interested in three supply current
(ICC) issues—standby, active, and transient current
peaks produced by falling and rising edges of chip-
enable. The capacitive and inductive loads on the
device outputs determine the magnitudes of these
peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 µF ceramic
capacitor connected between VCC and VSS, and
between VPP and VSS.
Place the high-frequency, low-inherent inductance
capacitors as close as possible to the devices.
Also, for every eight devices, a 4.7 µF electrolytic
capacitor should be placed at the array's power
supply connection, between VCC and VSS. The bulk
capacitor will overcome voltage slumps caused by
printed circuit board trace inductance, and will
supply charge to the smaller capacitors as needed.
3.3 VPP Trace on Printed Circuit
Boards
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the VPP power
supply trace. The VPP pin supplies the memory cell
current for programming. Use similar trace widths
and layout considerations given the VCC power bus.
Adequate VPP supply traces and decoupling will
decrease VPP voltage spikes and overshoots.
3.4 Power-Up/Down Protection
The 28F010 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F010 is
indifferent as to which power supply, VPP or VCC,
powers up first. Power supply sequencing is not
required. Internal circuitry in the 28F010 ensures
that the command register is reset to the read mode
on power-up.
A system designer must guard against active writes
for VCC voltages above VLKO when VPP is active.
Since both WE# and CE# must be low for a
command write, driving either to VIH will inhibit
writes. The control register architecture provides an
added level of protection since alteration of memory
contents only occurs after successful completion of
the two-step command sequences.
3.5 28F010 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F010 does not consume any power to retain
code or data when the system is off. Table 4
illustrates the power dissipated when updating the
28F010.
16










页数 30 页
下载[ TE28F010-150.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
TE28F010-15028F010 1024K (128K X 8) CMOS FLASH MEMORYIntel Corporation
Intel Corporation

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap