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PDF ( 数据手册 , 数据表 ) TE28F008C3T110

零件编号 TE28F008C3T110
描述 3 VOLT ADVANCED+ BOOT BLOCK 8-/ 16-/ 32-MBIT FLASH MEMORY FAMILY
制造商 Intel Corporation
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TE28F008C3T110 数据手册, 描述, 功能
E
PRODUCT PREVIEW
3 VOLT ADVANCED+ BOOT BLOCK
8-, 16-, 32-MBIT
FLASH MEMORY FAMILY
28F008C3, 28F016C3, 28F032C3
28F800C3, 28F160C3, 28F320C3
n Flexible SmartVoltage Technology
2.7 V–3.6 V Read/Program/Erase
2.7 V or 1.65 V I/O Option Reduces
Overall System Power
12 V for Fast Production
Programming
n High Performance
2.7 V–3.6 V: 90 ns Max Access Time
3.0 V–3.6 V: 80 ns Max Access Time
n Optimized Architecture for Code Plus
Data Storage
Eight 8-Kbyte Blocks,
Top or Bottom Locations
Up to Sixty-Three 64-KB Blocks
Fast Program Suspend Capability
Fast Erase Suspend Capability
n Flexible Block Locking
Lock/Unlock Any Block
Full Protection on Power-Up
WP# Pin for Hardware Block
Protection
VPP = GND Option
VCC Lockout Voltage
n Low Power Consumption
9 mA Typical Read Power
10 µA Typical Standby Power with
Automatic Power Savings Feature
n Extended Temperature Operation
–40 °C to +85 °C
n Easy-12 V
Faster Production Programming
No Additional System Logic
n 128-bit Protection Register
64-bit Unique Device Identifier
64-bit User Programmable OTP
Cells
n Extended Cycling Capability
Minimum 100,000 Block Erase
Cycles
n Flash Data Integrator Software
Flash Memory Manager
System Interrupt Manager
Supports Parameter Storage,
Streaming Data (e.g., voice)
n Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
n SRAM-Compatible Write Interface
n Cross-Compatible Command Support
Intel Basic Command Set
Common Flash Interface
n x 16 for High Performance
48-Ball µBGA* Package
48-Lead TSOP Package
n x 8 I/O for Space Savings
48-Ball µBGA* Package
40-Lead TSOP Package
n 0.25 µ ETOX™ VI Flash Technology
The 0.25 µm 3 Volt Advanced+ Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a
feature-rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage
capability (2.7 V read, program and erase) with high-speed, low-power operation. Flexible block locking
allows any block to be independently locked or unlocked. Add to this the Intel-developed Flash Data
Integrator (FDI) software and you have a cost-effective, flexible, monolithic code plus data storage solution on
the market today. 3 Volt Advanced+ Boot Block products will be available in 48-lead TSOP, 40-lead TSOP,
and 48-ball µBGA* packages. Additional information on this product family can be obtained by accessing
Intel’s WWW page: http://www.intel.com/design/flcomp.
May 1998
Order Number: 290645-001







TE28F008C3T110 pdf, 数据表
3 VOLT ADVANCED+ BOOT BLOCK
E
12345678
16M
A A13 A11 A8 VPP WP# A19 A7 A4
B A14 A10 WE# RP# A18 A17 A5 A2
32M
C A15 A12 A9 A20
A6 A3 A1
D
A16 D14
D5
D11 D2
D8 CE# A0
E VCCQ D15
D6
D12 D3
D9
D0 GND
F
GND D7 D13 D4 VCC D10 D1 OE#
NOTES:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A19 is the upgrade address for the 16-Mbit device. A20 is the
upgrade address for the 32-Mbit device.
2. 8-Mbit not available on µBGA* CSP.
Figure 3. x16 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
12345678
16M
A A14 A12 A8 VPP WP# A20 A7 A4
B A15 A10 WE# RP# A19 A18 A5
32M
C A16 A13 A9 A21
A6 A3
A2
A1
D A17 NC D5 NC D2 NC CE# A0
E VCCQ A11 D6 NC D3 NC D0 GND
F GND D7 NC D4 VCC NC D1 OE#
NOTES:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A20 is the upgrade address for the 16-Mbit device. A21 is the
upgrade address for the 32-Mbit device.
2. 8-Mbit not available on µBGA* CSP.
Figure 4. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
8 PRODUCT PREVIEW







TE28F008C3T110 equivalent, schematic
3 VOLT ADVANCED+ BOOT BLOCK
E
Table 6. Command Codes and Descriptions
Code Device Mode
Description
FF Read Array Places device in read array mode, such that array data will be output on the
data pins.
40
Program
This is a two-cycle command. The first cycle prepares the CUI for a program
Set-Up
operation. The second cycle latches addresses and data information and
initiates the WSM to execute the Program algorithm. The flash outputs status
register data when CE# or OE# is toggled. A Read Array command is required
after programming to read array data. See Section 3.2.5.
20
Erase
Prepares the CUI for the Erase Confirm command. If the next command is not
Set-Up
an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the
status register to a “1,” (b) place the device into the read status register mode,
and (c) wait for another command. See Section 3.2.6.
D0 Erase Confirm If the previous command was an Erase Set-Up command, then the CUI will
close the address and data latches, and begin erasing the block indicated on the
address pins. During program/erase, the device will respond only to the Read
Status Register, Program Suspend and Erase Suspend commands and will
output status register data when CE# or OE# is toggled.
Program/Erase If a program or erase operation was previously suspended, this command will
Resume
resume that operation.
Unlock Block
If the previous command was Configuration Set-Up, the CUI will latch the
address and unlock the block indicated on the address pins. If the block had
been previously set to Lock-Down, this operation will have no effect. (Sect. 3.3)
B0
Program
Issuing this command will begin to suspend the currently executing
Suspend
program/erase operation. The status register will indicate when the operation
Erase
Suspend
has been successfully suspended by setting either the program suspend (SR.2)
or erase suspend (SR.6) and the WSM Status bit (SR.7) to a “1” (ready). The
WSM will continue to idle in the SUSPEND state, regardless of the state of all
input control pins except RP#, which will immediately shut down the WSM and
the remainder of the chip if RP# is driven to VIL. See Sections 3.2.5.1 and
3.2.6.1.
70 Read Status This command places the device into read status register mode. Reading the
Register
device will output the contents of the status register, regardless of the address
presented to the device. The device automatically enters this mode after a
program or erase operation has been initiated. See Section 3.2.3.
50 Clear Status The WSM can set the Block Lock Status (SR.1) , V PP Status (SR.3), Program
Register
Status (SR.4), and Erase Status (SR.5) bits in the status register to “1,” but it
cannot clear them to “0.” Issuing this command clears those bits to “0.”
90
Read
Puts the device into the Read Configuration mode, so that reading the device
Configuration will output the manufacturer/device codes or block lock status. Section 3.2.2.
60 Configuration Prepares the CUI for changes to the device configuration, such as block locking
Set-Up
changes. If the next command is not Block Unlock, Block Lock, or Block Lock-
Down, then the CUI will set both the Program and Erase Status register bits to
indicate a command sequence error. See Section 3.3.
01 Lock-Block If the previous command was Configuration Set-Up, the CUI will latch the
address and lock the block indicated on the address pins. (Section 3.3)
16 PRODUCT PREVIEW










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