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PDF ( 数据手册 , 数据表 ) TE28F004S3-150

零件编号 TE28F004S3-150
描述 BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4/ 8/ AND 16 MBIT
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


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TE28F004S3-150 数据手册, 描述, 功能
E
PRELIMINARY
BYTE-WIDE
SMART 3 FlashFile™ MEMORY FAMILY
4, 8, AND 16 MBIT
28F004S3, 28F008S3, 28F016S3
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology
Smart 3 Flash: 2.7 V or 3.3 V VCC
and 2.7 V, 3.3 V or 12 V VPP
n High-Performance
120 ns Read Access Time
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Write Lockout during Power
Transitions
n Enhanced Automated Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n Industry-Standard Packaging
40-Lead TSOP, 44-Lead PSOP
and 40 Bump µBGA* CSP
n High-Density 64-Kbyte Symmetrical
Erase Block Architecture
4 Mbit: Eight Blocks
8 Mbit: Sixteen Blocks
16 Mbit: Thirty-Two Blocks
n Extended Cycling Capability
100,000 Block Erase Cycles
n Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
n Automated Program and Block Erase
Command User Interface
Status Register
n SRAM-Compatible Write Interface
n ETOX™ V Nonvolatile Flash
Technology
Intel’s byte-wide Smart 3 FlashFile™ memory family renders a variety of density offerings in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile,
read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible
voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels
of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008SA architecture, the byte-wide Smart 3 FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
December 1997
Order Number: 290598-004







TE28F004S3-150 pdf, 数据表
BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY
E
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
VPP
RP#
A11
A10
A9
A8
A7
A6
A5
A4
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
VPP
RP#
A11
A10
A9
A8
A7
A6
A5
A4
NC
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
VPP
RP#
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28F016S3
28F008S3
28F004S3
40-LEAD TSOP
STANDARD PINOUT
10 mm x 20 mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Figure 2. TSOP 40-Lead Pinout
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
GND
GND
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ 4
VCC
GND
GND
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
GND
GND
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
8 PRELIMINARY







TE28F004S3-150 equivalent, schematic
BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY
E
4.1 Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to read
array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, program, or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or
Program Suspend command. The Read Array
command functions independently of the VPP
voltage and RP# can be VIH or VHH.
4.2 Read Identifier Codes
Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Figure 6 retrieve the manufacturer, device, block
lock configuration and master lock configuration
codes (see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the VPP voltage and RP# can be
VIH or VHH. Following the Read Identifier Codes
command, the subsequent information can be read.
Table 4. Identifier Codes
Code
Address Data
Manufacturer Code
000000
89
4-Mbit 000001
A7
Device Code
8-Mbit 000001
A6
16-Mbit 000001 AA
Block Lock Configuration XX0002(1)
Block Is Unlocked
DQ0 = 0
Block Is Locked
DQ0 = 1
Reserved for Future Use
DQ1–7
Master Lock Configuration 000003
Device Is Unlocked
DQ0 = 0
Device Is Locked
DQ0 = 1
Reserved for Future Use
DQ1–7
NOTE:
1. X selects the specific block lock configuration code to
be read. See Figure 5 for the device identifier code
memory map.
16
4.3 Read Status Register
Command
The status register may be read to determine when
a block erase, program, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs first. OE# or CE# must
toggle to VIH to update the status register latch. The
Read Status Register command functions
independently of the VPP voltage. RP# can be VIH
or VHH.
4.4 Clear Status Register
Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to “1”s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied VPP voltage. RP# can
be VIH or VHH. This command is not functional
during block erase or program suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
written first, followed by a block erase confirm. This
command sequence requires appropriate se-
quencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register
data when read (see Figure 7). The CPU can detect
block erase completion by analyzing the RY/BY#
pin or status register bit SR.7.
PRELIMINARY










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