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PDF ( 数据手册 , 数据表 ) TE28F004BEB120

零件编号 TE28F004BEB120
描述 4-MBIT (256K X 16/ 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
制造商 Intel Corporation
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TE28F004BEB120 数据手册, 描述, 功能
E
PRELIMINARY
4-MBIT (256K X 16, 512K X 8)
SmartVoltage BOOT BLOCK FLASH
MEMORY FAMILY
28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B
28F400CE-T/B, 28F004BE-T/B
n Intel SmartVoltage Technology
5V or 12V Program/Erase
2.7V, 3.3V or 5V Read Operation
Increased Programming Throughput
at 12V VPP
n Very High-Performance Read
5V: 60/80/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time
3V: 110/150/180 ns Max Access
65/90 ns Max. Output Enable Time
2.7V: 120 ns Max Access 65 ns Max.
Output Enable Time
n Low Power Consumption
Max 60 mA Read Current at 5V
Max 30 mA Read Current at
2.7V–3.6V
n x8/x16-Selectable Input/Output Bus
28F400 for High Performance 16- or
32-bit CPUs
n x8-Only Input/Output Architecture
28F004B for Space-Constrained
8-bit Applications
n Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Three 128-KB Main Blocks
Top or Bottom Boot Locations
n Absolute Hardware-Protection for Boot
Block
n Software EEPROM Emulation with
Parameter Blocks
n Extended Temperature Operation
–40°C to +85°C
n Extended Cycling Capability
100,000 Block Erase Cycles
(Commercial Temperature)
10,000 Block Erase Cycles
(Extended Temperature)
n Automated Word/Byte Program and
Block Erase
Industry-Standard Command User
Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
n Reset/Deep Power-Down Input
0.2 µA ICCTypical
Provides Reset for Boot Operations
n Hardware Data Protection Feature
Write Lockout during Power
Transitions
n Industry-Standard Surface Mount
Packaging
40-Lead TSOP
44-Lead PSOP: JEDEC ROM
Compatible
48-Lead TSOP
56-Lead TSOP
n Footprint Upgradeable from 2-Mbit and
to 8-Mbit Boot Block Flash Memories
n ETOX™ IV Flash Technology
July 1997
Order Number: 290530-005







TE28F004BEB120 pdf, 数据表
4-MBIT SmartVoltage BOOT BLOCK FAMILY
E
A[18:1]
CS#
RD#
WR#
i386™ EX CPU
(25 MHz)
D[0:15]
RESET
A[0:17]
CE#
OE#
WE#
28F400BV-60
DQ[0:15]
RP#
RESET
NOTE:
A data bus buffer may be needed for processor speeds above 25 MHz.
Figure 1. 28F400 Interface to Intel386™ EX Microprocessor
0530_01
A[16:18]
A8-A15
80C188EB
ALE
AD0-AD7
ADDRESS
LATCHES
LE
ADDRESS
LATCHES
LE
A0 -A18
28F004-T
UCS#
WR#
RD#
RESIN#
P1.X
System Reset
DQ 0 -DQ 7
CE#
VCC
10K
WE#
OE#
RP#
VCC
VPP
P1.X
WP#
Figure 2. 28F004B Interface to Intel80C188EB 8-Bit Embedded Microprocessor
0530_02
8 PRELIMINARY







TE28F004BEB120 equivalent, schematic
4-MBIT SmartVoltage BOOT BLOCK FAMILY
E
Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH)
Mode
Notes RP# CE# OE# WE# A9
A0 VPP
Read
1,2,3 VIH VIL VIL VIH
X
X
X
Output Disable
VIH VIL VIH VIH
X
X
X
Standby
VIH VIH
X
X
X
X
X
Deep Power-Down 9 VIL X X X X X X
Intelligent Identifier
(Mfr)
4 VIH VIL VIL VIH VID VIL X
Intelligent Identifier
(Device)
4,5 VIH VIL VIL VIH VID VIH
X
Write
6,7,8 VIH VIL VIH VIL
X
X
X
DQ0–15
DOUT
High Z
High Z
High Z
0089 H
See
Table 5
DIN
Mode
Read
Output
Disable
Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)
Notes RP# CE# OE# WE# A9
A0 A–1 VPP
1,2,3 VIH VIL VIL VIH
X
X
X
X
VIH VIL VIH VIH
X
X
X
X
DQ0–7
DOUT
High Z
DQ8–14
High Z
High Z
Standby
VIH VIH
X
X
X
X
X
X High Z High Z
Deep Power-
9
VIL X
X
X
X
X
X
X High Z High Z
Down
Intelligent
Identifier (Mfr)
4
VIH VIL VIL VIH VID VIL
X
X 89H High Z
Intelligent
Identifier
(Device)
4,5 VIH VIL VIL VIH VID VIH X
X See High Z
Table
5
Write
6,7,8 VIH VIL VIH VIL
X
X
X
X
DIN
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP.
3. See DC Characteristics for VPPLK, VPPH1, VPPH2, VHH, VID voltages.
4. Manufacturer and device codes may also be accessed via a CUI write sequence, A1–A17 = X, A1–A18 = X.
5. See Table 5 for device IDs.
6. Refer to Table 7 for valid DIN during a write operation.
7. Command writes for block erase or word/byte program are only executed when VPP = VPPH1 or VPPH2.
8. To write or erase the boot block, hold RP# at VHH or WP# at VIH. See Section 3.4.
9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
High Z
16 PRELIMINARY










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