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PDF ( 数据手册 , 数据表 ) TS68302VR16

零件编号 TS68302VR16
描述 Integrated Multiprotocol Processor IMP
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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TS68302VR16 数据手册, 描述, 功能
Features
TS68000/TS68008 Microprocessor Core Supporting a 16- or 8-bit TS68000 Family
System Integration Block Including:
– Independent Direct Memory Access (IDMA) Controller
– Interrupt Controller with Two Modes of Operation
– Parallel Input/output (I/O) Ports, some with Interrupt Capability
– On-chip Usable 1152 bytes of Dual-port Random-access Memory (RAM)
– Three Timers, including a Watchdog Timer
– Four Programmable Chip-select Lines with Wait-state Logic
– Programmable Address Mapping of Dual-port RAM and IMP Registers
– On-chip Clock Generator with an Output Clock Signal
– System Control:
System Control Register
Bus Arbitration Logic with Low Interrupt Latency Support
Hardware Watchdog for Monitoring Bus Activity
Low Power (Standby) Modes
Disable CPU Logic (TS68000)
Freeze Control for Debugging Selected On-chip Peripherals
DRAM Refresh Controller
Communications Processor Including:
– Main Controller (RISC Processor)
– Three Full-duplex Serial Communication Controllers (SCCs)
– Six Serial Direct Memory Access (SDMA) Channels Dedicated to the Three SCCs
– Flexible Physical Interface Accessible by SCCs for Interchip Digital Link (IDL)
General Circuit Interface (GCI, see note), Pulse Code Modulation (PCM), and
Nonmultiplexed Serial Interface (NMSI) Operation
– Serial Communication Port (SCP) for Synchronous Communication, Clock Rate up
to 4.096 MHz
– Serial Management Controllers (SMCs) for IDL and GCI Channels
Frequency of Operation: 16.67 MHz
Power Supply: 5 VDC ± 10%
Description
The IMP is a very large-scale integration (VLSI) device incorporating the main building
blocks needed for the design of a wide variety of controllers. The device is especially
suitable to applications in the communications industry. The IMP is the first device to
offer the benefits of a closely coupled, industry-standard, TS68000/TS68008 micro-
processor core and a flexible communications architecture. This multichannel
communications device may be configured to support a number of popular industry
interfaces, including those for the integrated services digital network (ISDN) basic rate
and terminal adapter applications. Through a combination of architectural and pro-
grammable features, concurrent operation of different protocols is easily achieved
using the IMP. Data concentrators, line cards, bridges, and gateways are examples of
suitable applications for this versatile device.
The IMP is a high-density complementary metal-oxide semiconductor (HCMOS)
device consisting of a TS68000/TS68008 microprocessor core, a system integration
block (SIB), and a communications processor (CP). The TS68302 block diagram is
shown in Figure 1.
Note: GCI is sometimes referred to as IOM2.
Integrated
Multiprotocol
Processor (IMP)
TS68302
Rev. 2117A–HIREL–11/02
1







TS68302VR16 pdf, 数据表
This device contains protective circuitry to protect the inputs against damage due to high
static voltages or electrical fields; however, it is advised that normal precautions be
taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to
an appropriate logic voltage level (e.g., either GND or VDD).
Figure 5. Clock Input Timing Diagram
tcyc
2.0V
0.8V
tr (C)
tf (C)
Note:
Timing measurements are referenced to and from a low voltage of 0.8V and a voltage of 2.0V, unless otherwise noted. The volt-
age swing through this range should start outside, and pass through, the range such that the rise or fall will be linear between
0.8V and 2.0V.
Table 4. Thermal Characteristics at 25°C
Package
Symbol Parameter
PGA 132
CERQUAD 132
θJA Thermal Resistance - Ceramic Junction To Ambient
θJC Thermal Resistance - Ceramic Junction To Case
θJA Thermal Resistance - Ceramic Junction To Ambient
θJC Thermal Resistance - Ceramic Junction To Case
Value
33
5
46
2
Unit
°C/W
°C/W
°C/W
°C/W
Power Considerations
The average chip-junction temperature, TJ, in °C can be obtained from:
TJ = TA + (PD ⋅ θJA)
(1)
TA = Ambient Temperature, °C
θJA = Package Thermal Resistance, Junction-to-Ambient, °C/W
PD = PINT + PI/O
PINT = ICC VCC, Watts - Chip Internal Power
PI/O = Power Dissipation on Input and Output pins - user determined
Note: For TA = 70°C and PD = 0.5 W at 12.5 MHz Tj = 88°C.
For most applications PI/O < 0,30 PINT and can be neglected.
An approximate relationship between PD and TJ (if PI/O is neglected) is:
PD = K ÷ (TJ + 273)
(2)
Solving equations (1) and (2) for K gives:
K = PD (TA + 273) + θJA PD2
(3)
where K is a constant pertaining to the particular part. K can be determined from equa-
tion (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the
values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any
value of TA.
8 TS68302
2117A–HIREL–11/02







TS68302VR16 equivalent, schematic
Figure 8. Write Cycle Timing Diagram
OUT
Notes:
1. Timing measurements are referenced to and from a low voltage of 0.8V and a high of 2.0V, unless otherwise noted. The
voltage swing through this range should start outside and pass through the range such that the rise and fall is linear between
0.8V and 2.0V.
2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge of S2 (specifica-
tion #20A).
16 TS68302
2117A–HIREL–11/02










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