DataSheet8.cn


PDF ( 数据手册 , 数据表 ) TZA3004HL

零件编号 TZA3004HL
描述 SDH/SONET data and clock recovery unit STM1/4 OC3/12
制造商 NXP Semiconductors
LOGO NXP Semiconductors LOGO 


1 Page

No Preview Available !

TZA3004HL 数据手册, 描述, 功能
INTEGRATED CIRCUITS
DATA SHEET
TZA3004HL
SDH/SONET data and clock
recovery unit STM1/4 OC3/12
Objective specification
File under Integrated Circuits, IC19
1998 Feb 09







TZA3004HL pdf, 数据表
Philips Semiconductors
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
Objective specification
TZA3004HL
Loop mode enable (ENL)
Loop mode is provided for system testing. Loop mode is
enabled by applying a voltage lower than 0.8 V (TTL LOW)
to the ENL pin. This selects loop mode outputs DLOOP,
DLOOPQ and CLOOP, CLOOPQ. If a voltage greater than
2.0 V (TTL HIGH) is applied to ENL, then DOUT, DOUTQ
and COUT, COUTQ are switched in while DLOOP,
DLOOPQ and CLOOP, CLOOPQ are disabled to minimize
power consumption. If ENL is connected to VEE (3.3 V),
all outputs are enabled.
External capacitor for loop filter (CAPUPQ; CAPDOQ)
The loop filter is an integrator with a built in capacitance of
2 × 130 pF. An external 200 nF capacitance must be
connected between CAPUPQ and CAPDOQ to ensure
loop stability while the frequency window detector is
active.
Lock detection (LOCK)
The LOCK pin should be interpreted as an indication if the
reference clock (CREF) is present and if the acquisition aid
(frequency window detector) is working properly. The
LOCK pin is an open collector TTL output and should be
pulled up with a 10kresistor to the positive supply. If the
VCO frequency is within a 1000 ppm window around the
desired frequency the LOCK pin will go HIGH. If no
reference clock is present, or the VCO is outside the 1000
ppm window, the LOCK pin will be LOW. The logic level of
LOCK does not indicate if the PLL is locked onto the
incoming data; this is indicated by the LOS signal.
STM mode selection (SEL155)
SEL155 should be connected to VEE for STM1/OC3
(155.52 Mbits/s) operation. For STM4/OC12
(622.08 Mbits/s) systems, SEL155 should be connected to
GND. The connections to VEE and GND should have low
resistance and inductance. Short PCB tracks are
recommended.
Table 1 STM Mode Select
MODE
STM1
STM4
BIT RATE
Mbits/s
155.52
622.08
DIV #
16
4
SEL155
VEE
GND
Loss-of-signal detection (LOS)
The Loss of Signal (LOS) function is closely related to the
Alexander Phase Detector functionality. Refer to Fig.3 for
the meaning of A,B and T in this section.
In the functional description it is described that the phase
detector doesn’t take any action if the value at sample
points A and B is the same, because there hasn’t been any
transition. However, if the values at A and B are the same,
but different from T, this still means there hasn’t been any
transition, but somehow T got the wrong value. This is
probably due to noise or bad signal integrity, which will
lead to a Bit Error. Hence the occurrence of this particular
situation is an indication for Bit Errors. If too many of these
Bit Errors occur per time and the PLL is gradually losing
lock, the LOS alarm is asserted. The LOS assert level is
around a Bit Error Rate (BER) of 5⋅10-2 and the de-assert
level is around BER of 1⋅10-3.
The LOS detection is BER related, but neither dependent
of datastream content, nor protocol. Therefore, a
SDH/SONET datastream is no prerequisite for a proper
LOS function. Since the LOS function of the TZA3004HL
is derived from digital signals, it is a good supplement to an
analog, amplitude based, LOS indication.
The LOS alarm is an open collector TTL compatible
output. A pull-up resistor should be connected to a positive
supply. LOS will be HIGH (TTL) if the data signal is absent
at DIN, DINQ or BER is > 5⋅10-2, otherwise it will be LOW
(BER < 1⋅10-3).
Reference frequency select (REF19, REF39)
A reference clock signal (either 19.44 MHz or 38.88 MHz,
whichever is available) must be connected to CREF and
CREFQ. Pins REF19 and REF39 are used to select the
appropriate output frequency at frequency divider 2. Since
the reference clock is only used as acquisition aid for the
PLL (Frequency Window Detector), the quality of the
reference clock is not important. There is no phase noise
specification imposed on the reference clock generator
and even frequency stability may be in the order of 100
ppm. In general most inexpensive crystal based oscillators
are suitable.
Table 2 Reference Frequency Select
FREQUENCY
MHz
38.88
19.44
DIV #
64
128
REF19
VEE
GND
REF39
VEE
VEE
1998 Feb 09
8







TZA3004HL equivalent, schematic
Philips Semiconductors
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
100
Objective specification
TZA3004HL
10
1
0.1
10
100
1000
10000
Fig.9 Jitter Tolerance in STM4 mode (622.08 Mbits/s). Measured on OM5800 demoboard
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Fig.10 Output waveforms on Data and Clock outputs in STM4 mode (622.08 Mbits/s). (single ended)
1998 Feb 09
16










页数 24 页
下载[ TZA3004HL.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
TZA3004HLSDH/SONET data and clock recovery unit STM1/4 OC3/12NXP Semiconductors
NXP Semiconductors

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap