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PDF ( 数据手册 , 数据表 ) VG4616322BQ-7R

零件编号 VG4616322BQ-7R
描述 262/144x32x2-Bit CMOS Synchronous Graphic RAM
制造商 Vanguard International Semiconductor
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VG4616322BQ-7R 数据手册, 描述, 功能
VIS
Overview
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
The VG4616321(2) SGRAM is a high-speed CMOS synchronous graphics RAM containing 16M bits. It
is internally configured as a dual 256K x 32 DRAM with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the 256K x 32 bit banks is organized as 1024 rows by
256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The VG4616321(2) provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page,
with burst termination option. An Auto Precharge function may be enabled to provide a self-timed row pre-
charge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh
are easy to use. In addition, it features the write per bit and the masked block write functions.
By having a programmable Mode register and special mode register, the system can choose the best
suitable modes to maximize its performance. These devices are well suited for applications requiring high
memory bandwidth, and when combined with special graphics functions result in a device particularly well
suited to high performance graphics applications.
Features
• Fast access time from clock: 4.5/5/5.5ns
• Fast clock rate: 200/166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• Dual internal banks(256K x 32-bit x 2-bank)
• Programmable Mode and Special Mode registers
- CAS Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst Read Single Write
- Load Color or Mask register
• Burst stop function
• Individual byte controlled by DQM0-3
• Block write and write-per-bit capability
• Auto Refresh and Self Refresh
• 2048 refresh cycles/32ms
• Single + 3.3V ±0.3V power supply
• Input Reference Voltage : Vref = 1.5V ± 0.2V
• Interface: LVTTL and SSTL_3
• JEDEC 100-pin Plastic QFP package
Document:1G5-0145
Rev.1
Page 1







VG4616322BQ-7R pdf, 数据表
VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
The Read command is used to read burst of data on consecutive clock cycles from an active row
in an active bank. The bank must be active for at least tRCD(min.) before Read command is issued.
During read bursts, the valid data-out element from the starting column address will be available
following the CAS latency after the issue of Read command. Each subsequent data-out element will
be valid by the next positive clock edge (refer to the following figure). The DQs goes into high-imped-
ance at the end of the burst, unless other command was initiated. The burst length, burst sequence,
and CAS latency are determined by the mode register which is already prgrammed.A full-page burst
will continue until terminated (at the end of the page it will wrap to column 0 and continue).
T0 T1 T2 T3 T4 T5 T6
T7 T8
CLK
COMMAND
READ A
CAS Iatency = 1
tCK1,DQ’s
CAS Iatency = 2
tCK2,DQ’s
CAS Iatency = 3
tCK3,DQ’s
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP
NOP
Burst Read Operation (Burst Length = 4, CAS Latency = 1, 2, 3)
The read data appears on the DQs subjects to the values on the DQM inputs two clocks early (i.e.
DQM latency is two clocks for output buffers). A read burst without auto precharge function may be
interrupted by a subsequent Read or Write/Block Write command to the same bank or the other
active bank before the end of burst length. It may be interrupted by a BankPrecharge/PrechargeAll
command to the same bank too. The interrupt comes from Read command can occur on any clock
cycle following a previous Read command (refer to the following figure).
CLK
T0 T1 T2 T3 T4 T5 T6
T7 T8
COMMAND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS Iatency = 1
tCK1,DQ’s
CAS Iatency = 2
tCK2,DQ’s
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
CAS Iatency = 3
tCK3,DQ’s
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
Read Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
The DQM inputs are used to avoid I/O contention on DQ pins when the interrupt comes from
Write/Block Write command. The DQMs must be asserted (High) at least two clocks prior to the
Write/Block Write command to suppress data-out on DQ pins. To guarantee DQ pins against the I/O
contention, a single cycle with high-impedance on DQ pins must occur between the last read data
and the Write/Block Write command (refer to the following three figures). If the data output of burst
read occurs at the second clock of burst write, the DQMs must be asserted (High) at least one clock
prior to the Write/Block Write command to avoid internal bus contention.
Document:1G5-0145
Rev.1
Page 8







VG4616322BQ-7R equivalent, schematic
VIS
CLK
CKE
CS
RAS
T0 T1
tCK2
Preliminary
T2 T3 T4 T5
Clock min
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
T6 T7 T8 T9 T10
CAS
WE
DSF
BS
A9
A0-A8
DQM
DQ Hi-Z
Address key
tRP
PrechargeAll
Mode Register Any
Set Command Command
Mode Register Set Cycle (CAS Latency = 1, 2, 3)
The mode register is divided into various fields depending on functionality.
• Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 1, 2, 4, 8, or full page.
A2 A1 A0
00
0
00
1
01
0
01
1
10
0
10
1
11
0
11
1
Burst Length
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Document:1G5-0145
Rev.1
Page 16










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VG4616322BQ-7R262/144x32x2-Bit CMOS Synchronous Graphic RAMVanguard International Semiconductor
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