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PDF ( 数据手册 , 数据表 ) VG36646141BT-10

零件编号 VG36646141BT-10
描述 CMOS Synchronous Dynamic RAM
制造商 Vanguard International Semiconductor
LOGO Vanguard International Semiconductor LOGO 


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VG36646141BT-10 数据手册, 描述, 功能
VIS
Description
Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 1,048,576 - word x 16-bit x 4-bank. it is
fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only
power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V (±0.3V ) power supply
• High speed clock cycle time : 8/10ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,&Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by A12 & A13 (Bank select)
• Each Bank can operate simultaneously and independently
• LVTTL compatible I/O interface
• Random column access in every cycle
• X16 organization
• Input/Output controlled by LDQM and UDQM
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0127
Rev2
Page 1







VG36646141BT-10 pdf, 数据表
VIS
Basic Features and Function Description
1.Simplified State Diagram
Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
Mode
Register
Set
MRS
IDLE
Self
Refresh
SELFSeEnLtFryexit
REF
AUTO
Refresh
CKE
Power
Down
ROW
ACTIVE
CKE
CKE
Active
Power
Down
Write (Write recovery)
Read
WRITE CKE
SUSPEND CKE
WRITE
Write with
Auto Precharge
WRITE A CKE
SUSPEND CKE
WRITE A
Read (write recovery)
AutoRPeraedchwaitrhge
Write
(writAeWurertoictoePvewreriytc)hharge
READ
CKE
CKE
READ
SUSPEND
Read with
Auto Precharge
CKE
READ A
CKE
READA
SUSPEND
POWER
ON
Precharge
Document : 1G5-0127
Precharge
Automatic sequence
Manual input
Note: After the AUTO refresh operation, precharge operation is
performed automatically and enter the IDLE state
Rev2
Page 8







VG36646141BT-10 equivalent, schematic
VIS
Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
6.Address Bits of Bank-Select and Precharge
6.1 Quad banks controlled by A12 & A13 (for VG36648041/VG36648042)
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
(Activate command)
A12 A13 Result
0 0 Select Bank A
“Activate “ command
0 1 Select Bank B
“Activate” command
1 0 Select Bank C
“Activate” command
1 1 Select Bank D
“Activate” command
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
(Precharge command)
A10 A12 A13 Result
0 0 0 Precharge Bank A
0 0 1 Precharge Bank B
0 1 0 Precharge Bank C
0 1 1 Precharge Bank D
1 X X Precharge All Banks
X: Don't care
0 Disables Auto - Precharge (End of Burst)
1 Enables Auto - Precharge (End of Burst)
Co1. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A12 A13 Result
(CAS strobes)
0 0 Enables Read/Write
commands for Bank A
0 1 Enables Read/Write
commands for Bank B
1 0 Enables Read/Write
commands for Bank C
1 1 Enables Read/Write
commands for Bank D
Document : 1G5-0127
Rev2
Page 16










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VG36646141BT-10CMOS Synchronous Dynamic RAMVanguard International Semiconductor
Vanguard International Semiconductor

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