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PDF ( 数据手册 , 数据表 ) VG36644041DT

零件编号 VG36644041DT
描述 CMOS Synchronous Dynamic RAM
制造商 Vanguard International Semiconductor
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VG36644041DT 数据手册, 描述, 功能
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
Description
The VG36644041D, VG36648041D and VG36641641D are high-speed 67,108,864-bit synchronous
dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4 and 1,048,576 x 16 x
4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input
and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible
with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
• Single 3.3V (±0.3V ) power supply
• High speed clock cycle time
-6 : 166MHz<3-3-3>, available only on 4MX16 option
-7 : 143MHz<3-3-3>, 133MHz<2-3-2>
-7L: 133MHz<3-3-3>
-8H: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by A12 & A13 (Bank Select)
• Byte control by LDQM and UDQM for VG36641641D
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X4, X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge command
Document :1G5-0177
Rev.2
Page 1







VG36644041DT pdf, 数据表
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
A.C. Characteristics (Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter
Sym-
bol
CLK cycle time
CL = 3
CL = 2
CLK to valid output CL = 3
delay
CL = 2
CLK high pulse width
CLK low pulse width
CKE setup time
CKE hold time
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
Data input hold time
Output data hold
time
CL = 3
CL = 2
CLK to output in low - Z
CLK to output in H - Z
ROW cycle time
ROW active time
RAS to CAS delay
Row precharge time
Row active to active delay
Data in to precharge
Transition time
Mode reg. set cycle
Refresh time
tCK3
tCK2
tAC3
tAC2
tCH
tCL
tCKS
tCKH
tAS
tAH
tCMS
tCMH
tDS
tDH
tOH3
tOH2
tLZ
tHZ
tRC
tRAS
tRCD
tRP
tRRD
tDPL
tT
tRSC
tREF
-6 *1
Min Max
6
7.5
5
6
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2.5
2.5
0
2.5 5
60
42 100K
18
15
12
12
1 10
2
64
Limits
-7 -7L
Min Max Min Max
7 7.5
7.5 10
5.4 5.4
66
2.5 2.5
2.5 2.5
1.5 1.5
0.8 0.8
1.5 1.5
0.8 0.8
1.5 1.5
0.8 0.8
1.5 1.5
0.8 0.8
2.7 2.7
2.7 3
00
2.7 5.4 2.7 5.4
63 67.5
42 100K 45 100K
20 20
15 20
14 15
14 15
1 10 1 10
22
64 64
-8H Unit Note
Min Max
8 ns
10 ns
6 ns *2
6 ns *2
3 ns
3 ns
2 ns
1 ns
2 ns
1 ns
2 ns
1 ns
2 ns
1 ns
3 ns *2
3 ns *2
0 ns
3 6 ns
70 ns
50 100K ns
20 ns
20 ns
20 ns
20 ns
1 10 ns
2 tck
64 ms
Notes
1. -6 grade is available only on 4MX16 option.
2. if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
Document :1G5-0177
Rev.2
Page 8







VG36644041DT equivalent, schematic
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
5.Mode Register
13 12 11 10 9 8 7 6 5 4 3 2 1 0
00 0 0 0 0 1
13 12 11 10 9 8 7 6 5 4 3 2 1 0
x x x x 1 0 0 LTMODE WT
BL
13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 LTMODE WT
BL
JEDEC Standard Test Set
Burst Read and Single Write (for Write Through Cache)
Burst Read and Burst Write
X = Don’t care
Burst length
Wrap type
Bits2 - 0 WT = 0 WT = 1
000 1 1
001 2
010 4
011 8
2
4
8
100 R R
101 R R
110 R
111 Fullpage
R
R
0 Sequential
1 Interleave
Latency
mode
Bits 6-4 CAS Iatency
000 R
001 R
010 2
011 3
100 R
101 R
110 R
111 R
Remark R : Reserved
Document :1G5-0177
Rev.2
Page 16










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Vanguard International Semiconductor

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