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PDF ( 数据手册 , 数据表 ) VG36643241BT-8

零件编号 VG36643241BT-8
描述 CMOS Synchronous Dynamic RAM
制造商 Vanguard International Semiconductor
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VG36643241BT-8 数据手册, 描述, 功能
VIS
Description
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 -
bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively. lt is fabricated with an advanced
submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is
packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V (±0.3V ) power supply
• High speed clock cycle time : 8/10 for LVTTL
• High speed clock cycle time : 8/10 for SSTL - 3
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Dual Internal banks controlled by A11 (Bank select) for VG36643211(2)
• Quad Internal banks controlled by A11 & A12 (Bank select) for VG36643241(2)
• Each Banks can operate simultaneously and independently
• LVTTL compatible I/O interface for VG36643211 and VG36643241
• SSTL - 3 compatible I/O interface for VG36643212 and VG36643242
• Random column access in every cycle
• x32 organization
• Input/Output controlled by DQM0 ~ 3
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
Document : 1G5-0099
Rev.1
Page 1







VG36643241BT-8 pdf, 数据表
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
A.C Characteristics : (Ta = 0 to 70°C VDD = 3.3V ± 0.3V, VSS = 0V)
Parameter
CLK cycle time (1)
CLK to valid output delay
CLK high pulse width
CLK low pulse width
CKE setup time
CKE hold time
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
CAS
Latency symbol
3 tck3
2 tck2
3 tAc3
2 tAc2
tCH
tCL
tCKS
tCKH
tAS
tAH
tCMS
tCMH
tDS
VG3664321 (4) 1 (2) B
-8H -8L
-10
Min Max Min Max Min Max
8 8 10
10 12
15
66 6
66 6
33
3
33
3
22
3
11
1
22
3
11
1
22
3
11
1
22
3
Data input hold time
tDH 1
1
1
Output data hold time
CLK to output in low - Z
CLK to output in Hi - Z
tOH 3
3
3
tLZ 0
0
0
3 tHZ
6
6
6
2 66 6
CLK to output in Hi - Z without load
tOHN
1
1
2
Row active to active delay
RAS to CAS delay
Row precharge time
ROW active time
ROW cycle time
Last data in to burst stop
tRRD 16
16
20
tRCD 20
20
26
tRP 20
20
26
tRAS 48 120K 48 120K 60 120K
tRC 70
70
90
tBDL
1
1
1
Data - in to ACT(REF) command
Data - in to precharge
Transition time
Mode reg. set cycle
Self refresh exit time
Refresh time
tDAL 1+ tRP
1+ tRP
1+ tRP
tDPL
8
8
10
tT(1) 1 10 1 10 1 10
tT(2) 0.2
5
0.2
5
0.2
5
tRSC
2
2
2
tSRX
1
1
1
tREF
64
64
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
ns
ns
CLK
CLK
ms
Notes : (1) The input clock should be stable and continuous. (jitter 7% * tCK)
Document : 1G5-0099
Rev.1
Page 8







VG36643241BT-8 equivalent, schematic
VIS
5.1 Burst Length and Sequence
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
(Burst of Two)
Starting Address
(column address A0, binary)
0
1
(Burst of Four)
Starting Address
(column address A1 - A0, binary)
00
01
10
11
Sequential Addressing
Sequence (decimal)
0, 1
1, 0
Sequential Addressing
Sequence (decimal)
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
Interleave Addressing Sequence (decimal)
0, 1
1, 0
Interleave Addressing Sequence (decimal)
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
(Burst of Eight)
Starting Address
(column address A2 - A0, binary)
000
001
010
011
100
101
110
111
Sequential Addressing
Sequence (decimal)
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1 ,2
4, 5, 6, 7, 0, 1, 2, 3
5, 6 ,7, 0, 1, 2, 3, 4
6, 7 ,0 ,1 ,2 ,3 ,4 ,5
7, 0, 1, 2, 3, 4, 5, 6
Interleave Addressing Sequence(decimal)
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length
being 256 for 4B 2M x 32, and 512 for 2B 2M x 32.
Document : 1G5-0099
Rev.1
Page 16










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