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PDF ( 数据手册 , 数据表 ) VG36128801A

零件编号 VG36128801A
描述 CMOS Synchronous Dynamic RAM
制造商 Vanguard International Semiconductor
LOGO Vanguard International Semiconductor LOGO 


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VG36128801A 数据手册, 描述, 功能
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Description
The device is CMOS Synchronous Dynamic RAM organized as 8,388,608 - word x 4 -bit x 4 - bank,
4,194,304 - word x 8 - bit x 4 - bank, or 2,097,152 - word x 16 - bit x 4 - bank. These various organizations
provide wide choice for different applications. It is designed with the state-of-the-art technology to meet stan-
dard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the perfor-
mance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.
Features
• Single 3.3V ( ±0.3V) power supply
• High speed clock cycle time : 7.5ns/10ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by BA0 & BA1 (Bank select)
• Each Bank can be operated simultaneously and independently
• I/O level : LVTTL compatible
• Random column access in every cycle
• x4, x8, x16 organization
• Input/Output controlled by DQM ( LDQM, UDQM )
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0154
Rev.1
Page 1







VG36128801A pdf, 数据表
VIS
Basic Features and Function Description
1.Simplified State Diagram
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Mode
Register
Set
MRS
IDLE
Self
Refresh
SELFSeEnLtFryexit
REF
AUTO
Refresh
CKE
CKE
Power
Down
ROW
ACTIVE
CKE
CKE
Active
Power
Down
Write (Write recovery)
WRITE CKE
SUSPEND CKE
WRITE
Write with
Auto Precharge
WRITEA CKE
SUSPEND CKE
WRITEA
Write
rite recovery
W
Read (write recovery)
Read
AutoRPeraedchwaitrhge
Write
(writAeRureetoacodPvewreryict)hharge
Read
READ
CKE
CKE
READ
SUSPEND
Read with
Auto Precharge
READA
CKE
CKE
READA
SUSPEND
POWER
ON
Precharge
Document : 1G5-0154
Precharge
Automatic sequence
Manual input
Note: After the AUTO refresh operation, precharge operation is
performed automatically and enter the IDLE state.
Rev.1
Page 8







VG36128801A equivalent, schematic
VIS
Preliminary
6 Address Bits of Bank-Select and precharge
6.1 Quad banks controlled by A12 & A13
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
(Activate command)
A12 A13 Result
0
0
Select Bank A
“Activate “ command
0
1
Select Bank B
“Activate” command
1
0
Select Bank C
“Activate” command
1
1
Select Bank D
“Activate” command
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Row
(Precharge command)
A10 A12 A13 Result
0 0 0 Precharge Bank A
0 0 1 Precharge Bank B
0 1 0 Precharge Bank C
0 1 1 Precharge Bank D
1 X X Precharge All Banks
0 Disables Auto - Precharge (End of Burst)
1 Enables Auto - Precharge (End of Burst)
Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A12 A13 Result
(CAS strobes)
0
0
Enables Read/Write
commands for Bank A
0
1
Enables Read/Write
commands for Bank B
1
0
Enables Read/Write
commands for Bank C
1
1
Enables Read/Write
commands for Bank D
Document : 1G5-0154
Rev.1
Page 16










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