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PDF ( 数据手册 , 数据表 ) VG36128401BT

零件编号 VG36128401BT
描述 CMOS Synchronous Dynamic RAM
制造商 Vanguard International Semiconductor
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VG36128401BT 数据手册, 描述, 功能
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Description
The VG36128401B, VG36128801B and VG3664128161B are high-speed 134,217,728-bit synchro-
nous dynamic random-access memories, organized as 8,388,608 x 4 x 4, 4,194,304 x 8 x 4 and 2,097,152 x
16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input
and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible
with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
• Single 3.3V (±0.3V ) power supply
• High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by BA0 & BA1 (Bank Select)
• Byte control by LDQM and UDQM for VG36128161DT
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X4, X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
.
Document :1G5-0183
Rev.1
Page 1







VG36128401BT pdf, 数据表
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
A.C. Characteristics (Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter
Symbol
CLK cycle time
CLK to valid output delay
CLK high pulse width
CLK low pulse width
Input setup time (all input)
Input hold time (all input)
Output data hold time
CLK to output in low - Z
CLK to output in H - Z
ROW cycle time
ROW active time
RAS to CAS delay
Row precharge time
Row active to active delay
Write recovery time
Transition time
Mode reg. set cycle
Power down exit setup time
Self refresh exit time
Refresh time
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
tCK3
tCK2
tAC3
tAC2
tCH
tCL
tIS
tIH
tOH3
tOH2
tLZ
tHZ
tRC
tRAS
tRCD
tRP
tRRD
tWR
tT
tRSC
tPDE
tSRX
tREF
-7H
Min Max
7.5
7.5
5.4
5.4
2.5
2.5
1.5
0.8
2.7
2.7
0
2.7 5.4
67.5
45 100K
15
15
14
14
1 10
14
7
7
64
Limits
-7L
Min Max
7.5
10
5.4
6
2.5
2.5
1.5
0.8
2.7
3
0
2.7 5.4
67.5
45 100K
20
20
15
15
1 10
15
7.5
7.5
64
-8H
Min Max
10
8
6
6
3
3
2
1
3
3
0
36
70
50 100K
20
20
20
20
1 10
20
10
10
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Document :1G5-0183
Rev.1
Page 8







VG36128401BT equivalent, schematic
VIS
5. Mode Register
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 LTMODE WT
BL
Burst length
Wrap type
Bits2 - 0 WT = 0 WT = 1
000 1 1
001 2
010 4
011 8
2
4
8
100 R R
101 R R
110 R
111 Fullpage
R
R
0 Sequential
1 Interleave
Latency
mode
Bits 6-4 CAS Iatency
000 R
001 R
010 2
011 3
100 R
101 R
110 R
111 R
Remark R : Reserved
Document :1G5-0183
Rev.1
Page 16










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Vanguard International Semiconductor

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