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PDF ( 数据手册 , 数据表 ) VG26V17400EJ-5

零件编号 VG26V17400EJ-5
描述 4/194/304 x 4 - Bit CMOS Dynamic RAM
制造商 Vanguard International Semiconductor
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VG26V17400EJ-5 数据手册, 描述, 功能
VIS
Description
VG26(V)(S)17400E
4,194,304 x 4 - Bit
CMOS Dynamic RAM
The device is CMOS Dynamic RAM organized as 4,194,304 words x 4 bits. It is fabricated
with an advanced submicron CMOS technology and designed to operate from a single 5V only
or 3.3V only power supply. Low voltage operation is more suitable to be used on battery
backup, portable electronic application. A new refresh feature called “ self-refresh “ is supported
and very slow CBR cycles are being performed. It is packaged in JEDEC standard 26/24 - pin
plastic SOJ or TSOP (II).
Features
• Single 5V (±10 %) or 3.3V (±10 %) only power supply
• High speed tRAC access time : 50/60 ns
• Low power dissipation
- Active mode : 5V version 605/550 mW (Max.)
3.3V version 396/360 mW (Max.)
- Standby mode : 5V version 1.375 mW (Max.)
3.3V version 0.54 mW (Max.)
• Fast Page Mode access
• I/O level : TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
• 2048 refresh cycles in 32 ms (Std) or 128ms (S - version)
• 4 refresh mode :
- RAS only refresh
- CAS-before-RAS refresh
- Hidden refresh
- Self - refresh (S - version)
Document : 1G5-0142
Rev.1
Page 1







VG26V17400EJ-5 pdf, 数据表
VIS
DC Characteristics ; 3.3 - Volt Verion
(Ta = 0 to 70°C, VCC = + 3.3V± 10%, Vss = 0V)
Parameter
Symbol
Test Conditions
Operating
current
Low
power
S - version
Standby Standard
Current power
version
RAS - only
refresh current
Fast page mode
current
CAS - before - RAS
refresh current
Self - refresh currant
(S - Version)
CAS - before - RAS
long refresh
current (S - Version)
RAS cycling
ICC1 CAS cycling
tRC = min.
LVTTL interface
RAS, CAS = VIH
Dout = high - Z
CMOS interface
RAS, CAS VCC - 0.2V
Dout = high - Z
ICC2 LVTTL interface
RAS, CAS = VIH
Dout = high - Z
CMOS interface
RAS, CAS VCC - 0.2V
Dout = high - Z
ICC3
RAS cycling, CAS = VIH
tRC = min.
ICC4
tPC = min.
ICC5 tRC = min.
RAS, CAS cycling
ICC8 tRASS 100µS
ICC9 Standby : VCC - 0.2V RAS
CAS before RAS refresh :
2048 cycles/128ms
RAS, RAS : 0V VIL 0.2V
VCC - 0.2V VIH VIH (Max)
Dout = high - Z, tRAS 300ns
VG26(V)(S)17400E
4,194,304 x 4 - Bit
CMOS Dynamic RAM
VG26 (V) (S) 17400E
-5 -6 Unit Notes
Min Max Min Max
- 110 - 100 mA 1, 2
- 0.5
- 0.5
mA
- 0.25
- 0.25
mA
-2-2
mA
- 0.5
- 0.5
mA
- 110
- 80
- 110
- 250
- 300
- 100
1, 2
mA
- 70
1,3
mA
- 100
1, 2
mA
- 250 µA
- 300 µA
Document : 1G5-0142
Rev.1
Page 8







VG26V17400EJ-5 equivalent, schematic
VIS
• Delayed Write Cycle
RAS
CAS
tT
tRC
t RAS
tRCD
tCSH
tRSH
tCAS
VG26(V)(S)17400E
4,194,304 x 4 - Bit
CMOS Dynamic RAM
tRP
tCRP
tCPN
ADDRESS
WE
OE
DQ1 ~ DQ4
tASR
tRAH
Row
tASC
tCAH
Column
t RCS
t CWL
t RWL
tWP
t OED
t DS
tOEH
OPEN
tDS
tDH
DIN
Document : 1G5-0142
Rev.1
Page 16










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