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PDF ( 数据手册 , 数据表 ) VG26S18165CJ-6

零件编号 VG26S18165CJ-6
描述 1/048/576 x 16 - Bit CMOS Dynamic RAM
制造商 Vanguard International Semiconductor
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VG26S18165CJ-6 数据手册, 描述, 功能
VIS
Description
VG26(V)(S)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access
mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single
5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup,
portable electronic application. A new refresh feature called “self-refresh” is supported and very slow CBR
cycles are being performed. lt is packaged in JEDEC standard 42-pin plastic SOJ.
Features
• Single 5V(±10 %) or 3.3V(±10 %) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
- Active wode : 5V version 660/605 mW (Mas)
3.3V version 432/396 mW (Mas)
- Standby mode: 5V version 1.375 mW (Mas)
3.3V version 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
• 1024 refresh cycle in 16 ms(Std.) or 128 ms(S-version)
• 4 refresh modes:
- RAS only refresh
- CAS - before - RAS refresh
- Hidden refresh
- Self-refresh(S-version)
Document:1G5-0147
Rev.1
Page 1







VG26S18165CJ-6 pdf, 数据表
VIS
VG26(V)(S)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
DC Characteristics ; 3.3 - Volt Version
(Ta = 0 to 70°C, VCC = + 3.3V ±10 %, VSS = 0V)
Parameter
Symbol
Test Conditions
Operating current
Low
power
S-version
Standby
Current
Standard
power
version
RAS- only refresh current
EDO page mode current
CAS- before- RAS refresh
current
Self- refresh current
(S-Version)
CAS- before- RAS long
refresh current
(S-Version)
ICC1 RAS cycling
LCAS / UCAS cycling
tRC = min
ICC2 LVTTL interface
RAS, LCAS / UCAS = VIH
Dout = High-Z
CMOS interface
RAS, CAS VCC -0.2V
Dout = High-Z
LVTTL interface
RAS, LCAS / UCAS = VIH
Dout = High-Z
CMOS interface
RAS, CAS VCC -0.2V
Dout = High-Z
ICC3 RAS cycling
LCAS / UCAS = VIH
tRC = min
ICC4 tPC = min
ICC5
ICC8
tRC = min
RAS, LCAS / UCAS cycling
tRASS 100µs
ICC9 Standby: VCC- 0.2V RAS
CAS before RAS refresh:
2048 cycles / 128ms
RAS, LCAS / UCAS :
0V VIL 0.2V
VCC- 0.2V VIH VIH (max)
Dout = High-Z, tRAS 300ns
VG26(V)(S)18165C Unit Notes
-5 -6
Min Max Min Max
- 120
- 110 mA 1, 2
- 0.5
- 0.5 mA
- 0.15
- 0.15 mA
- 2 - 2 mA
- 0.5
- 0.5 mA
- 120
- 110 mA 1, 2
- 90
- 120
- 250
- 300
- 80 mA 1, 3
- 110 mA 1, 2
- 250 µA
- 300 µA
Document:1G5-0147
Rev.1
Page 8







VG26S18165CJ-6 equivalent, schematic
VIS
VG26(V)(S)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
• Byte Read Cycle
RAS
UCAS
(or LCAS)
LCAS
(or UCAS)
ADDRESS
WE
OE
DQ9~DQ16
(or DQ1~DQ8)
DQ1~DQ8
(or DQ9~DQ16)
tRC
t RAS
tRP
tCSH
tCRP
tRCD
tT
tRSH
tCAS
tASR
tRAD
tRAH
tASC
tRAL
tCAH
Row
Column
tRCS
tRRH
tRCH
tRAC
tOEA
tCAC
tAA
tCLZ
High-Z
tOEZ
tOFF
DOUT
Document:1G5-0147
Rev.1
Page 16










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