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PDF ( 数据手册 , 数据表 ) V53C317405A

零件编号 V53C317405A
描述 4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM
制造商 Mosel Vitelic Corp
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V53C317405A 数据手册, 描述, 功能
MOSEL VITELIC
V53C317405A
4M X 4 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C317405A
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Extended Data Out Page Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
Features
s 4M x 4-bit organization
s EDO Page Mode for a sustained data rate
of 50 MHz
s RAS access time: 50, 60, 70 ns
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh
s Refresh Interval: 2048 cycles/32 ms
s Available in 24/26-pin 300 mil SOJ,
and 24/26-pin 300 mil TSOP-II
s Single +3.3 V ±10% Power Supply
s TTL Interface
50
50 ns
25 ns
20 ns
84 ns
60
60 ns
30 ns
25 ns
104 ns
Description
The V53C317405A is a 4,194,304 x 4 bit high-
performance CMOS dynamic random access
memory. The V53C317405A offers Page mode
operation with Extended Data Output. The
V53C317405A has a symmetric address, 11-bit row
and 11-bit column.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 2048 x 4 bits,
within a page, with cycle times as short as 20ns.
These features make the V53C317405A ideally
suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
KT
••
V53C317405A Rev. 0.2 September 1998
Access Time (ns)
50 60
••
1
Power
Std.
Temperature
Mark
Blank







V53C317405A pdf, 数据表
MOSEL VITELIC
V53C317405A
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC5 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a EDO
page mode cycle
5) An initial pause of 200 ms is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum
of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured
between VIH and VIL.
8) Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined
by the latter of tRAC, tCAC, tCAA,tCPA, tOEA . tCAC is measured from tristate.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced
to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electri-
cal characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit
(high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle
is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions
is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in
read-write cycles.
V53C317405A Rev. 0.2 September 1998
8







V53C317405A equivalent, schematic
MOSEL VITELIC
Waveforms of RAS Only Refresh Cycle
RAS
VIH
VIL
CAS
VIH
VIL
Address
VIH
VIL
I/O
(Outputs)
VOH
VOL
tRAH
tASR
Row
“H” or “L”
tRAS
tRC
HI-Z
V53C317405A
tRP
tRPC
tCRP
tASR
Row
WL9
V53C317405A Rev. 0.2 September 1998
16










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