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PDF ( 数据手册 , 数据表 ) V53C16256H

零件编号 V53C16256H
描述 256K x 16 FAST PAGE MODE CMOS DYNAMIC RAM
制造商 Mosel Vitelic Corp
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V53C16256H 数据手册, 描述, 功能
MOSEL VITELIC
V53C16256H
256K x 16 FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Fast Page Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
30
30 ns
16 ns
19 ns
65 ns
35
35 ns
18 ns
21 ns
70 ns
40
40 ns
20 ns
23 ns
75 ns
45
45 ns
22 ns
25 ns
80 ns
50
50 ns
24 ns
28 ns
90 ns
60
60 ns
30 ns
35 ns
110 ns
Features
s 256K x 16-bit organization
s Fast Page Mode for a sustained data rate
of 53 MHz.
s RAS access time: 30, 35, 40, 45, 50, 60 ns
s Dual CAS Inputs
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s Refresh Interval: 512 cycles/8 ms
s Available in 40-pin 400 mil SOJ and
40/44L-pin 400 mil TSOP-II packages
s Single +5V ±10% Power Supply
s TTL Interface
Description
The V53C16256H is a 262,144 x 16 bit high-
performance CMOS dynamic random access mem-
ory. The V53C16256H offers Fast Page mode with
dual CAS inputs. An address, CAS and RAS input
capacitances are reduced to one quarter when the
x4 DRAM is used to construct the same memory
density. The V53C16256H has symmetric address
and accepts 512 cycle 8ms interval.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 512 x 16 bits,
within a page, with cycle times as short as 19ns.
The V53C16256H is best suited for graphics, and
DSP applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
-40°C to +85°C
Package Outline
KT
••
••
30
Access Time (ns)
35 40 45 50
••••
••••
Power
Temperature
60 Std.
Mark
• • Blank
••
I
V53C16256H Rev. 2.3 June 1998
1







V53C16256H pdf, 数据表
MOSEL VITELIC
V53C16256H
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two
transitions per address cycle in Fast Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ³ VSS and VIH (max.) £ VCC.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to one TTL input and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD £ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD ex-
ceeds tRAD (max.).
9. Assumes that tRCD £ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ³ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 ms pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C16256H Rev. 2.3 June 1998
8







V53C16256H equivalent, schematic
MOSEL VITELIC
Functional Description
The V53C16256H is a CMOS dynamic RAM op-
timized for high data bandwidth, low power applica-
tions. It is functionally similar to a traditional
dynamic RAM. The V53C16256H reads and writes
data by multiplexing an 18-bit address into a 9-bit
row and a 9-bit column address. The row address is
latched by the Row Address Strobe (RAS). The col-
umn address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be end-
ed or aborted before the minimum tRAS time has ex-
pired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS opera-
tion. The column address must be held for a mini-
mum specified by tAR. Data Out becomes valid only
when tOAC, tRAC, tCAA and tCAC are all satisifed. As
a result, the access time is dependent on the timing
relationships between these parameters. For exam-
ple, the access time is limited by tCAA when tRAC,
tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column ad-
dress is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
V53C16256H
Fast Page Mode Operation
Fast Page Mode operation permits all 512 col-
umns within a selected row of the device to be ran-
domly accessed at a high data rate. Maintaining
RAS low while performing successive CAS cycles
retains the row address internally and eliminates the
need to reapply it for each cycle. The column ad-
dress buffer acts as a transparent or flow-through
latch while CAS is high. Thus, access begins from
the occurrence of a valid column address rather
than from the falling edge of CAS, eliminating tASC
and tT from the critical timing path. CAS latches the
address into the column address buffer and acts as
an output enable. During Fast Page Mode opera-
tion, Read, Write, Read-Modify-Write or Read-
Write-Read cycles are possible at random address-
es within a row. Following the initial entry cycle into
Fast Page Mode, access is tCAA or tCAP controlled.
If the column address is valid prior to the rising edge
of CAS, the access time is referenced to the CAS
rising edge and is specified by tCAP. If the column
address is valid after the rising CAS edge, access
is timed from the occurrence of a valid address and
is specified by tCAA. In both cases, the falling edge
of CAS latches the address and enables the output.
Fast Page Mode provides a sustained data rate of
53 MHz for applications that require high data rates
such as bit-mapped graphics or high-speed signal
processing. The following equation can be used to
calculate the maximum data rate:
Data Rate = t--R----C-----+-----55---11----21-----´----t--P----C--
Data Output Operation
The V53C16256H Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition en-
ables the transfer of data to and from the selected
row address in the Memory Array. A RAS high tran-
sition disables data transfer and latches the output
data if the output is enabled. After a memory cycle
is initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level dis-
ables the I/O path and the output driver if it is en-
abled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output driv-
ers. The output drivers, when otherwise enabled,
can be disabled by holding OE high. The OE signal
has no effect on any data stored in the output latch-
es. A WE low level can also disable the output driv-
ers when CAS is low. During a Write cycle, if WE
goes low at a time in relationship to CAS that would
V53C16256H Rev. 2.3 June 1998
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