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PDF ( 数据手册 , 数据表 ) VIPer20ASP

零件编号 VIPer20ASP
描述 SMPS PRIMARY I.C.
制造商 STMicroelectronics
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VIPer20ASP 数据手册, 描述, 功能
VIPer20/SP/DIP
® VIPer20A/ASP/ADIP
SMPS PRIMARY I.C.
TYPE
VIPer20/SP/DIP
V I Per2 0A/ A SP/ AD IP
V DSS
6 20V
7 00V
In
0.5 A
0.5 A
RDS(on)
16
18
FEATURE
s ADJUSTABLE SWITCHING FREQUENCY UP
TO 200KHZ
s CURRENT MODE CONTROL
s SOFT START AND SHUT DOWN CONTROL
s AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
”BLUE ANGEL” NORM (<1W TOTAL POWER
CONSUMPTION)
s INTERNALLY TRIMMED ZENER
REFERENCE
s UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
s INTEGRATED START-UP SUPPLY
s AVALANCHE RUGGED
s OVERTEMPERATURE PROTECTION
s LOW STAND-BY CURRENT
s ADJUSTABLE CURRENT LIMITATION
DESCRIPTION
VIPer20/20A, made
BLOCK DIAGRAM
using
VIPower
M0
PENTAWATT HV PENTAWATT HV (022Y)
10
1
PowerSO-10
DIP-8
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (620V or 700V / 0.5A).
Typical applications cover off line power supplies
with a secondary power capability of 10W in wide
range condition and 20W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode without extra components.
OSC
DRAIN
November 1999
VDD
ON/OFF
OSCILLATOR
UVLO
LOGIC
SECURITY
LATCH
R/S FF Q
S
PWM
LATCH
S
R1 FF Q
R2 R3
OVERTEMP.
DETECTOR
0.5 V
ERROR
AMPLIFIER
_
+
_
13 V +
4.5V
1.7
µs
delay
250 ns
Blanking
COMP
0.5V
++ _
6 V/A
_
CURRENT
AMPLIFIER
SOURCE
1/21







VIPer20ASP pdf, 数据表
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 9: Oscillator
Rt
Ct
8/21
OSC
VDD
1
For RT > 1.2 K:
FSW
=
2.3
RT CT
DMAX
CLK
DMAX
=
1
550
RT 150
Recommended DMAX values:
100KHz: > 80%
200KHz: > 70%
FC00050
Maximum duty cycle vs Rt
FC00040
0.9
0.8
0.7
0.6
0.5
1
1,000
23
5 10
Rt (k)
20 30 50
Oscillator frequency vs Rt and Ct
FC00030
Ct = 1.5 nF
500
300
Ct = 2.7 nF
Ct = 4.7 nF
200
Ct = 10 nF
100
50
30
1
23
5
10 20 30 50
Rt (k)







VIPer20ASP equivalent, schematic
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 22: Recommended layout
From input
diodes bridge
C1
R1 2
VDD
1 OSC
13V
-
+
U1
VIPerXX0
3
DRAIN
COMP SOURCE
54
R2
C2
C3
ISO1
C4
T1
D2
D1
To sec ondary
C7
filtering and load
C5
C6
FC00500
LAYOUT CONSIDERATIONS
Some simple rules insure a correct running of
switching power supplies. They may be classified
into two categories:
- To minimise power loops: the way the switched
power current must be carefully analysed and
the corresponding paths must present the
smallest inner loop area as possible. This
avoids radiated EMC noises, conducted EMC
noises by magnetic coupling, and provides a
better efficiency by eliminating parasitic
inductances, especially on secondary side.
- To use different tracks for low level signals and
power ones. The interferences due to a mixing
of signal and power may result in instabilities
and/or anomalous behaviour of the device in
case of violent power surge (Input
overvoltages, output short circuits...).
In case of VIPer, these rules apply as shown on
figure 22. The loops C1-T1-U1, C5-D2-T1,
C7-D1-T1 must be minimised. C6 must be as
close as possible from T1. The signal
components C2, ISO1, C3 and C4 are using a
dedicated track to be connected directly to the
source of the device.
16/21










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