DataSheet8.cn


PDF ( 数据手册 , 数据表 ) VIC068A-BC

零件编号 VIC068A-BC
描述 VMEbus Interface Controller
制造商 Cypress Semiconductor
LOGO Cypress Semiconductor LOGO 


1 Page

No Preview Available !

VIC068A-BC 数据手册, 描述, 功能
VIC068A
Features
• Complete VMEbus interface controller and arbiter
— 58 internal registers provide configuration control
and status of VMEbus and local operations
— Drives arbitration, interrupt, address modifier utility,
strobe, address lines A07 through A01 and data lines
D07 through D00 directly, and provides signals for
control logic to drive remaining address and data
lines
— Direct connection to 68xxx family and mappable to
non-68xxx processors
Complete master/slave capability
— Supports read, write, write posting, and block trans-
fers
— Accommodates VMEbus timing requirements with
internal digital delay line (12-clock granularity)
— Programmable metastability delay
— Programmable data acquisition delays
— Provides timeout timers for local bus and VMEbus
transactions
Interleaved block transfers over VMEbus
— Acts as DMA master on local bus
— Programmable burst count, transfer length, and in-
terleaved period interval
— Supports local module-based DMA
Arbitration support
— Supports single-level, priority and round robin arbi-
tration
— Supports fair request option as requester
Interrupt support
— Complete support for the VMEbus interrupts: inter-
rupter and interrupt handler
VMEbus Interface Controller
— Seven local interrupt lines
— 8-level interrupt priority encode
— Total of 29 interrupts mapped through the VIC068A
Miscellaneous features
— Refresh option for local DRAM
— Four broadcast location monitors
— Four module-specific location monitors
— Eight interprocessor communications registers
— PGA or QFP packages
— Compatible with IEEE Specification 1014, Rev. C
— Supports RMC operations
See the VMEbus Interface Handbook for more informa-
tion
Functional Description
The VMEbus interface controller (VIC068A) is a single chip
designed to minimize the cost and board area requirements
and to maximize performance of the VMEbus interface of a
VMEbus master/slave module. This can be implemented on
VIC068A either an 8-bit, 16-bit, or 32-bit VMEbus system. The
VIC068A performs all VMEbus system controller functions
plus many others, which simplify the development of
VIC068Aa VMEbus interface. The VIC068A utilizes patented
on-chip output buffers. These CMOS high-drive buffers pro-
vide direct connection to the address and data lines. In addi-
tion to these signals, the VIC068A connects directly to the ar-
bitration, interrupt, address modifier, utility and strobe lines.
Signals are provided which control data direction and latch
functions needed for a 32-bit implementation.
The VIC068A was developed through the efforts of a consor-
tium of board vendors, under the auspices of the VMEbus In-
ternational Trade Association (VITA). The VIC068A thus in-
sures compatibility between boards designed by different
manufacturers.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1990 - Revised July 23, 1997







VIC068A-BC pdf, 数据表
VIC068A
slave accesses, the VIC068A decodes the AM codes and
checks the slave select control registers to see if the slave
request is to be supported with regard to address spaces, su-
pervisory accesses, and block transfers. The VIC068A also
supports user-defined AM codes; that is, the VIC068A can be
made to assert and respond to user-defined AM codes.
VIC068A VMEbus Block Transfers
The VIC068A is capable of both master and slave block trans-
fers. The master VIC068A performs a block transfer in one of
two modes:
• MOVEM-type Block Transfer
• Master Block Transfer with Local DMA
In addition to these VMEbus block transfers, the VIC068A is
also capable of performing block transfers from one local re-
source to another in a DMA-like fashion. This is referred to as
a Module-based DMA transfer.
The VMEbus specification restricts block transfers from cross-
ing 256-byte boundaries without toggling the address strobe,
in addition to restricting the maximum length of the transfer to
256 bytes. The VIC068A allows for easy implementation of
block transfers that exceed the 256-byte restriction by releas-
ing the VMEbus at the appropriate time and rearbitrating for
the bus at a programmed time later (this in-between time is
referred to as the interleave period), while at the same time
holding both the local and VMEbus addresses with internal
latches. All of this is performed without processor/software in-
tervention until the transfer is complete.
The VIC068A contains two separate address counters for the
VMEbus and the local address buses. In addition, a separate
address is counter-provided for slave block transfers. The
VIC068A address counters are 8-bit up-counters that provide
for transfers up to 256 bytes. For transfers that exceed the
256-byte limit, the Cypress CY7C964 or external counters and
latches are required.
The VIC068A allows slave accesses to occur during the inter-
leave period. Master accesses are also allowed during inter-
leave with programming and external logic. This is referred to
as the “dual path” option.
MOVEM Master Block Transfer
This mode of block transfer provides the simplest implementa-
tion of VMEbus block transfers. For this mode, the local re-
source simply configures the VIC068A for a MOVEM block
transfer and proceeds with the consecutive-address cycles
(such as a 680X0 MOVEM instruction). The local resource
continues as the local bus master in this mode.
Master Block Transfers with Local DMA
In this mode, the VIC068A becomes the local bus master and
reads or writes the local data in a DMA-like fashion. This pro-
vides a much faster interface than the MOVEM block transfer,
but with less control and fault tolerance.
VIC068A Slave Block Transfer
The process of receiving a block transfer is referred to as a
slave block transfer. The VIC068A is capable of decoding the
address modifier codes to determine that a slave block transfer
is desired. In this mode, the VIC068A captures the VMEbus
address, and latches them into internal counters. For subse-
quent cycles, the VIC068A simply increments this counter for
each transfer. The local protocol for slave block transfers can
be configured in a full handshake mode by toggling both PAS*
and DS* and expecting DSACKi* to toggle, or in an accelerat-
ed mode in which only DS* toggles and PAS* is asserted
throughout the cycle.
Module-Based DMA Transfers
The VIC068A is capable of acting as a DMA controller be-
tween two local resources. This mode is similar to that of mas-
ter block transfers with local DMA, with the exception that the
VMEbus is not the second source or destination.
VIC068A Interrupt Generation and Handling Facilities
The VIC068A is capable of generating and handling a sev-
en-level prioritized interrupt scheme similar to that used by the
Motorola CISC processors. These interrupts include the seven
VMEbus interrupts, seven local interrupts, five VIC068A er-
ror/status interrupts, and eight interprocessor communication
interrupts.
The VIC068A can be configured to act as handler for any of
the seven VMEbus interrupts. The VIC068A can generate the
seven VMEbus interrupts as well as supplying a user-defined
status/ID vector. The local priority level (IPL) for VMEbus inter-
rupts is programmable. When configured as the system con-
troller, the VIC068 will drive the IACK daisy-chain.
The local interrupts can be configured with the following:
• User-defined local interrupt priority level (IPL)
• Option for VIC068A to provide the status/ID vector
• Edge or level sensitivity
• Polarity (rising/falling edge, active HIGH/LOW)
The VIC068A is also capable of generating local interrupts on
certain error or status conditions. These include:
• ACFAIL* asserted
• SYSFAIL* asserted
• Failed master write-post (BERR* asserted)
• Local DMA completion for block transfers
• Arbitration timeout
• VMEbus interrupter interrupt
The VIC068A can also interrupt on the setting of a module or
global switch in the interprocessor communication facilities.
Interprocessor Communication Facilities
The VIC068A includes interprocessor registers and switches
that can be written and read through VMEbus accesses.
These are the only such registers that are directly accessible
from the VMEbus. Included in the interprocessor communica-
tion facilities are:
• Four general purpose 8-bit registers
• Four module switches
• Four global switches
• VIC068A version/revision register (read-only)
• VIC068A Reset/Halt condition (read-only)
• VIC068A interprocessor communication register sema-
phores
When set through a VMEbus access, these switches can in-
terrupt a local resource. The VIC068A includes module switch-
es that are intended for a single module, and global switches
which are intended to be used as a broadcast.
8














页数 15 页
下载[ VIC068A-BC.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
VIC068A-BCVMEbus Interface ControllerCypress Semiconductor
Cypress Semiconductor

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap