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PDF ( 数据手册 , 数据表 ) X76F041AE-3

零件编号 X76F041AE-3
描述 PASS TM SecureFlash
制造商 Xicor
LOGO Xicor LOGO 


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X76F041AE-3 数据手册, 描述, 功能
APPLICATION NOTE
A V A I LABLE
AN83 • Development Tools XK76C
Password Access Security Supervisor
4K
X76F041
4 x 128 x 8 Bit
PASSTM SecureFlash
FEATURES
• 64-Bit Password Security
• Three Password Modes
—Secure Read Access
—Secure Write Access
—Secure Configuration Access
• Programmable Configuration
—Read, Write and Configuration Access
Passwords
—Multiple Array Access/Functionality
—Retry Register/Counter
• 8 Byte Sector Write
• (4) 1K Memory Arrays
• ISO Response to Reset
• Low Power CMOS
—50µA Standby Current
—3mA Active Current
• 1.8V to 3.6V or 5V “Univolt” Read and Program
Power Supply Versions
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
—ESD Protection: 2000V on All Pins
DESCRIPTION
The X76F041 is a password access security supervisor
device, containing four 128 x 8 bit SecureFlash arrays.
Access can be controlled by three 64-bit programmable
passwords, one for read operations, one for write opera-
tions and one for device configuration.
The X76F041 features a serial interface and software
protocol allowing operation on a simple two wire bus. The
bus signals are a clock input (SCL) and a bidirectional
data input and output (SDA). Access to the device is con-
trolled through a chip select input (CS), allowing any
number of devices to share the same bus.
The X76F041 also features a synchronous response to
reset; providing an automatic output of a pre-configured
32-bit data stream conforming to the ISO standard for
memory cards.
The X76F041 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per sector and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
CS
SCL
SDA
RETRY
COUNTER
INTERFACE
LOGIC
RST
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7002-2.2 4/30/97 T3/C0/D0 SH
CHIP
ENABLE
DATA
TRANSFER
ARRAY ACCESS
ENABLE
PASSWORD ARRAY AND
PASSWORD VERIFICATION
LOGIC
ISO RESET RESPONSE
DATA REGISTER
CONFIGURATION
REGISTER
1
000–07F
080–0FF
100–17F
180–1FF
(4) 16 x 64
SECUREFLASH
ARRAYS
7002 ILL F01
Characteristics subject to change without notice







X76F041AE-3 pdf, 数据表
X76F041
ACK Polling
Once a stop condition is issued to indicate the end of the
host’s write sequence, the X76F041 initiates the internal
nonvolatile write cycle. In order to take advantage of the
typical 5ms write cycle, ACK polling can be initiated
immediately. This involves issuing the Start condition fol-
lowed by the new command code of eight bits (1st byte of
the protocol). If the X76F041 is still busy with the nonvol-
atile write operation, it will issue a “no ACK” in response.
If the nonvolatile write operation has completed, an
“ACK” will be returned and the host can then proceed
with the rest of the protocol. Refer to the following flow:
ACK Polling Sequence
WRITE SEQUENCE
COMPLETED
ENTER ACK POLLING
ISSUE
A START
After a password sequence, there is always a nonvolatile
write cycle. In order to continue the transaction, the
X76F041 requires the master to perform an ACK polling
with the specific code of C0h. As with regular acknowl-
edge polling the user can either time out for 10ms, and
then issue the ACK polling once, or continuously loop as
described in the flow.
As with regular acknowledge polling, if the user chooses
to loop, then as long as the nonvolatile write cycle is
active, a no ACK will be issued in response to each poll-
ing cycle.
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile write cycle is
over, in response to the ACK polling cycle immediately
following it.
If the password that was inserted was incorrect, then a
“no ACK” will be returned even if the nonvolatile write
cycle is over. Therefore, the user cannot be certain that
the password is incorrect until the 10ms write cycle time
has elapsed.
ISSUE NEW
COMMAND CODE
(1ST BYTE)
ACK
RETURNED
NO ACK (SDA HIGH)
YES (SDA LOW)
PROCEED
7002 ILL F12A
Figure 7. Acknowledge Polling
SCL
8th clk.
of 8th
pwd. byte
‘ACK’
clk
SDA
‘ACK’
START
condition
8th
clk
8th
bit
8
ACK
clk
ACK or
no ACK
7002 ILL F11







X76F041AE-3 equivalent, schematic
X76F041
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Read & Write Cycle Limits
Symbol
fSCL
TI
tDV
tLOW
tHIGH
tSTAS1
tSTAS2
tSTAH1
tSTAH2
tSTPS1
tSTPS2
tSTPH1
tSTPH2
tHD:DAT
tSU:DAT
tRSCL(4)
tFSCL(4)
tR(4)
tF(4)
tDH
tHZ1
tLZ
tVCCS
tSU:CS
tHD:CS
tHZ2
tSU:SCL
tRST
tSU:RST
fSCL:RST
tLOW:RST
tHIGH:RST
tPD
tNOL
tWC
Parameter
SCL Clock Frequency
Noise Suppression Time Constant at SCL & SDA Inputs
SCL HIGH to SDA Data Valid
Clock LOW Period
Clock HIGH Period
Start Condition Setup Time to Rising Edge of SCL
Start Condition Setup Time to Falling Edge of SCL
Start Condition Hold Time to Rising Edge of SCL
Start Condition Hold Time to Falling Edge of SCL
Stop Condition Setup Time to Rising Edge of SCL
Stop Condition Setup Time to Falling Edge of SCL
Stop Condition Hold Time to Rising Edge of SCL
Stop Condition Hold Time to Falling Edge of SCL
Data in Hold Time
Data in Setup Time
SCL Rise Time
SCL Fall Time
SDA, CS, RST Rise Time
SDA, CS, RST Fall Time
Data Out Hold Time
SCL LOW to High Impedance
SCL HIGH to Output Active
VCC to CS Setup Time
CS Setup Time
CS Hold Time
CS Deselect Time
SCL Setup Time to CS LOW after Power Up
RST HIGH Time
RST Setup Time
SCL Frequency During Response to Reset
SCL LOW Time During Response to Reset
SCL HIGH Time During Response to Reset
SCL LOW to SDA Valid During Response to Reset
RST to SCL Non-Overlap
Nonvolatile Write Cycle
Min.
500
500
150
150
50
50
150
150
50
50
10
150
0
0
5
200
100
200
1500
500
500
500
500
Max.
1
20
450
90
90
90
90
150
150
1
450
10
NOTES: (4) This parameter is periodically sampled and not 100% tested.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ms
7002 FRM T10
16










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