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PDF ( 数据手册 , 数据表 ) X68C75J

零件编号 X68C75J
描述 Port Expander and E2 Memory
制造商 Xicor
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X68C75J 数据手册, 描述, 功能
APPLICATION NOTES
AVA I L A B L E
X68C7AN562S• ALNI6C4 •®ANE662 • AN74
SLIC X68C75 SLIC® E2 Microperipheral
Port Expander and E2 Memory
FEATURES
• Highly Integrated Microcontroller Peripheral
—8K x 8 E2 Memory
—2 x 8 General Purpose Bidirectional I/O Ports
—16 x 8 General Purpose Registers
—Integerated Interrupt Controller Module
—Internal Programmable Address Decoding
• Self Loading Integrated Code (SLIC)
—On-Chip BIOS and Boot Loader
—IBM/PC Based Interface Software(XSLIC)
• Concurrent Read During Write
—Dual Plane Architecture
• Isolates Read/Write Functions Between
Planes
• Allows Continuous Execution Of Code
From One Plane While Writing In The
Other Plane
• Multiplexed Address/Data Bus
—Direct Interface to Popular 68HC11 Family of
Microcontrollers
• Software Data Protection
—Protect Entire Array During Power-up/-down
• Block Lock™ Data Protection
—Set Write Lockout in 1K Blocks
• Toggle Bit Polling
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
• 60mA Active
• 100µA Standby
• PDIP, PLCC, and TQFP Packaging Available
DESCRIPTION
The X68C75 is a highly integrated peripheral for the
68HC11 family of microcontrollers. The device inte-
grates 8K-bytes of 5V byte-alterable nonvolatile memory,
2 bidirectional 8-bit ports, 16 general purpose registers,
programmable internal address decoding and a multi-
plexed address and data bus.
The 5V byte-alterable nonvolatile memory can be used
as program storage, data storage, or a combination of
both. The memory array is separated into two 4K-byte
sections which allows read accesses to one section
while a write operation is taking place in the other
section. The nonvolatile memory also features Software
Data Protection to protect the contents during power
transitions, and an advanced Block Protect register
which allows individual blocks of the memory to be
configured as read-only or read/write.
PIN CONFIGURATIONS
DIP
RESET
A12
WC
SEL
STRA
A15
NC
A14
A13
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
X68C75
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
VCC
R/W
AS
A8
A9
A11
NC
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
NC
E
A10
CE
A/D7
A/D6
A/D5
2899 ILL F01
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
2899-2.1 4/11/97 T0/C0/D1 SH
PLCC
TQFP
INDEX
CORNER
A14
A13
PA7
PA6
PA5
PA44
PA3
33
PA2
PA1
PA0
A/D0
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 X68C75 35
12 SLIC 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
A11
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
2899 ILL F02.3
Concurrent Read During Write, Block Lock, and SLIC® E2 are registered trademarks of Xicor, Inc.
1 Characteristics subject to change without notice







X68C75J pdf, 数据表
X68C75 SLIC® E2
Programmable Address Decoding
The X68C75 features an internal programmable ad-
dress decoder which allows the nonvolatile memory
array and the internal registers to be mapped in various
locations of the 64K-byte memory map. The register set
is mappable into a 1K-byte block, while the nonvolatile
memory array is mappable into an 8K-byte block. The
mapping is controlled by two nonvolatile configuration
registers, the SFR Map Register and the E2 Memory
Map Register. Their bits are mapped as follows:
SFR Map Register (SFRM) Default = 81
76
10
A15-A10
5
A15
4
A14
3
A13
2
A12
10
A11 A10
2899 ILL F08
A15-A10 are upper address bits for the 1K-byte page
where the SFR memory is mapped.
BITS 7:6
Setting these two bits to any combination other than “10”
will interfere with device proper operation.
E2 Memory Map Register (EEM) Default = 07
7 6 543 21 0
0 0 LAM 0 RST A15 A14 A13
2899 ILL F09
A15-A13
Modifying these three bits changes the location of the
program memory within the address map.The A15-A13
correspond to the upper three address bits of the 8K-
byte page where program memory will be mapped.
RST
The RST bit controls the polarity of the RESET input pin.
“0” = RESET is Active LOW
“1” = RESET is Active HIGH
LAM
Port B can be configured as either a general purpose
I/O port (normal I/O mode), or latched address mode
(LAM). The LAM option programs port B to output the
demultiplexed low order byte of the address latched into
the X68C75 by AS. The LAM bit selects between these
two modes.
“0” = Port B is an I/O Port
“1” = Port B outputs low address byte (A7-A0)
Setting the Mapping Registers
The mapping registers are written using a modified
version of the Software Data Protection sequence. All
timings must adhere to the normal Software Data
Protection sequence.
Figure 8. Setting the SFR Map Register
AA b2 b1 b0 P 555
55 b2 b1 b0 P AAA
A0 b2 b1 b0 P 555
AA b2 b1 b0 P 555
D0 b2 b1 b0 P AAA
Desired
Value
b2 b1 b0 P XXX
Delay of tWC
Exit Routine
X = Don’t Care
B[2:0] = E2M [2:0]
P = Address bit (A12) of the
memory plane not being read.
2899 ILL F10.1
Figure 9. Setting Program Memory Map Register
AA b2 b1 b0 P 555
55 b2 b1 b0 P AAA
A0 b2 b1 b0 P 555
AA b2 b1 b0 P 555
E0 b2 b1 b0 P AAA
Desired
Value
b2 b1 b0 P XXX
Delay of tWC
Exit Routine
X = Don’t Care
B[2:0] = E2M [2:0]
P = Address bit (A12) of the
memory plane not being read.
2899 ILL F11.1
8







X68C75J equivalent, schematic
X68C75 SLIC® E2
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS .................................. –1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this speci-
fication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
0°C
+70°C
X68C75
5V ±10%
Industrial
–40°C
+85°C
2899 PGM T05.1
Military
–55°C
+125°C
2899 PGM T04.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max. Units
Test Conditions
ICC VCC Current (Active)
60 mA
ISB1(CMOS) VCC Current (Standby)
100 µA
ISB2(TTL) VCC Current (Standby)
2 mA
ILI Input Leakage Current
ILO Output Leakage Current
10 µA
10 µA
VlL(3)
VIH(3)
VOL
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
–1 0.8 V
2 VCC + 0.5 V
0.4 V
VOH
Output HIGH Voltage
2.4
V
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Test
Max.
CE = VIH, All I/O’s = Open, Other
Inputs = VCC
CE = VIL, All I/O’s = Open, Other
Inputs = VCC–0.3V, AS = VIL
CE = VIL, All I/O’s = Open, Other
Inputs = VIH, AS = VIL
VIN = VSS to VCC
VOUT = VSS to VCC,
E = VIL
IOL = 2.1mA,
Ports (A,B) IOL = 20mA
IOH = –400µA
2899 PGM T06.1
Units
Conditions
CI/O(4)
CIN(4)
POWER-UP TIMING
Input/Output Capacitance
Input Capacitance
10 pF
6 pF
VI/O = 0V
VIN = 0V
2899 PGM T07
Symbol
Parameter
Max.
Units
tPUR(4)
tPUW(4)
Power-Up to Read
Power-Up to Write
Notes: (3) VIL min. and VIH max. are for reference only and are not tested.
(4) This parameter is periodically sampled and not 100% tested.
1
5
ms
ms
2899 PGM T08
16










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