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PDF ( 数据手册 , 数据表 ) X40626V14

零件编号 X40626V14
描述 Dual Voltage CPU Supervisor with 64K Serial EEPROM
制造商 Xicor
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X40626V14 数据手册, 描述, 功能
Preliminary Information
64K
X40626
8K x 8 Bit
Dual Voltage CPU Supervisor with 64K Serial EEPROM
FEATURES
• Dual voltage monitoring
—V2Mon operates independent of VCC
• Watchdog timer with selectable timeout intervals
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—User programmable VTRIP threshold
—Reset signal valid to VCC=1V
• Low power CMOS
—20µA max standby current, watchdog on
—1µA standby current, watchdog OFF
• 64Kbits of EEPROM
—64 byte page size
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lockprotection
• 400kHz 2-wire interface
—Slave addressing supports up to 4 devices on
the same bus
• 2.7V to 5.5V power supply operation
• Available Packages
—14-lead SOIC
—14-lead TSSOP
DESCRIPTION
The X40626 combines four popular functions, Power-on
Reset Control, Watchdog Timer, Dual Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to stabi-
lize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontrol-
ler fails to restart a timer within a selectable time-out
interval, the device activates the RESET signal. The user
selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the set minimum VCC trip
point. RESET is asserted until VCC returns to proper
BLOCK DIAGRAM
V2MON
WP
SDA
SCL
S0
S1
V2 Monitor
Logic
+
VTRIP2
-
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
64KB
EEPROM
Array
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
V2FAIL
RESET
Power on and
Low Voltage
VCC
+ Reset
VTRIP
-
Generation
REV 1.1.15 2/11/04
www.xicor.com
Characteristics subject to change without notice. 1 of 23







X40626V14 pdf, 数据表
X40626
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 6.
Serial Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.
Figure 6. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 7.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
REV 1.1.15 2/11/04
www.xicor.com
Characteristics subject to change without notice. 8 of 23







X40626V14 equivalent, schematic
X40626
CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V)
Symbol
COUT(4)
CIN (4)
Parameter
Output Capacitance (SDA, RESET, V2FAIL)
Input Capacitance (SCL, WP, S0, S1)
Notes: (4) This parameter is periodically sampled and not 100% tested.
Max.
8
6
Units
pF
pF
Test Conditions
VOUT = 0V
VIN = 0V
EQUIVALENT A.C. LOAD CIRCUIT
SDA
RESET
5V
1533
30pF
V2MON
1.53K
V2FAIL
30pF
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
0.1VCC to 0.9VCC
10ns
0.5VCC
Standard Output Load
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Symbol
fSCL
tIN
tAA
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
tR
tF
tSU:WP
tHD:WP
Cb
Parameter
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
WP Hold Time
Capacitive load for each bus line
Min.
0
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 + 0.1Cb(2)
20 + 0.1Cb(2)
0.6
0
Max.
400
0.9
300
300
400
Notes: (1) Typical values are for TA = 25°C and VCC = 5.0V
(2) Cb = total capacitance of one bus line in pF.
Units
KHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
REV 1.1.15 2/11/04
www.xicor.com
Characteristics subject to change without notice. 16 of 23










页数 23 页
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