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PDF ( 数据手册 , 数据表 ) X4005M8-1.8

零件编号 X4005M8-1.8
描述 CPU Supervisor
制造商 Xicor
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X4005M8-1.8 数据手册, 描述, 功能
X4003/X4005
CPU Supervisor
FEATURES
• Selectable watchdog timer
—Select 200ms, 600ms, 1.4s, off
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—12µA typical standby current, watchdog on
—800nA typical standby current watchdog off
—3mA active current
• 400kHz I2C interface
• 1.8V to 5.5V power supply operation
• Available packages
—8-lead SOIC
—8-lead MSOP
BLOCK DIAGRAM
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Watchdog Timer, and Supply Voltage
Supervision. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
microcontroller fails to restart a timer within a select-
able time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available; however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements, or to fine-tune the thresh-
old for applications requiring higher precision.
WP
SDA
SCL
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Control
Register
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
RESET (X4003)
RESET (X4005)
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 1 of 18







X4005M8-1.8 pdf, 数据表
X4003/X4005
Figure 7. Acknowledge Response From Receiver
SCL from
Master
1
Data Output
from Transmitter
Data Output
from Receiver
Start
89
Acknowledge
SERIAL WRITE OPERATIONS
Slave Address Byte
Following a start condition, the master must output a
slave address byte. This byte consists of several parts:
– a device type identifier that is always ‘1011’.
– two bits of ‘0’.
– one bit of the slave command byte is a R/W bit. The
R/W bit of the slave address byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 8.
– After loading the entire slave address byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct com-
pare, the device outputs an acknowledge on the SDA
line.
Write Control Register
To write to the control register, the device requires the
slave address byte and a byte address. This gives the
master access to register. After receipt of the address
byte, the device responds with an acknowledge, and
awaits the data. After receiving the 8 bits of the data
byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating
a stop condition, at which time the device begins the
internal write cycle to the nonvolatile memory. During
this internal write cycle, the device inputs are disabled,
so the device will not respond to any requests from the
master. If WP is HIGH, the control register cannot be
changed. A write to the control register will suppress
the acknowledge bit and no data in the control register
will change. With WP low, a second byte written to the
control register terminates the operation and no write
occurs.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending 1 full data byte
plus the subsequent ACK signal. If a stop is issued in
the middle of a data byte, or before 1 full data byte plus
its associated ACK is sent, then the device will reset
itself without performing the write.
Figure 8. Write Control Register Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
Address
Byte
Address
10 11 0 010 1111111 1
AA
CC
KK
Data
A
C
K
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 8 of 18







X4005M8-1.8 equivalent, schematic
X4003/X4005
PACKAGING INFORMATION
8-Lead Miniature Small Outline Gull Wing Package Type M
0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)
0.118 ± 0.002
(3.00 ± 0.05)
0.0256 (0.65) Typ.
0.118 ± 0.002
(3.00 ± 0.05)
R 0.014 (0.36)
0.030 (0.76)
0.0216 (0.55)
0.036 (0.91)
0.032 (0.81)
7° Typ.
0.040 ± 0.002
(1.02 ± 0.05)
0.008 (0.20)
0.004 (0.10)
0.007 (0.18)
0.005 (0.13)
0.150 (3.81)
Ref.
0.193 (4.90)
Ref.
0.220"
0.0256" Typical
0.025"
Typical
FOOTPRINT
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
0.020"
Typical
8 Places
REV 1.1.3 4/30/02
www.xicor.com
Characteristics subject to change without notice. 16 of 18










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