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PDF ( 数据手册 , 数据表 ) XC1701

零件编号 XC1701
描述 Serial Configuration PROMs
制造商 Xilinx
LOGO Xilinx LOGO 


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XC1701 数据手册, 描述, 功能
®
December 10, 1997 (Version 1.1)
0
XC1701L (3.3V), XC1701 (5.0V) and
XC17512L (3.3V)
Serial Configuration PROMs
0 5* Product Specification
Features
• On-chip address counter, incremented by each rising
edge on the clock input
• Simple interface to the FPGA; requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active Low)
for compatibility with different FPGA solutions
• Supports XC4000EX/XL fast configuration mode (15.0
MHz)
• Low-power CMOS Floating Gate process
• Available in 5 V and 3.3 V versions
• Available in compact plastic packages: 8-pin PDIP,
20-pin SOIC, and 20-pin PLCC.
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
Description
The XC1701L, XC1701 and XC17512L serial configuration
PROMs (SCPs) provide an easy-to-use, cost-effective
method for storing Xilinx FPGA configuration bitstreams.
When the FPGA is in master serial mode, it generates a
configuration clock that drives the SCP. A short access time
after the rising clock edge, data appears on the SCP DATA
output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
SCP. When the FPGA is in slave mode, the SCP and the
FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SCPs in this chain
are interconnected. All devices are compatible and can be
cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to the programmer.
VCC VPP GND
CE
RESET/
OE or
OE/
RESET
CLK
Address Counter
TC
EPROM
Cell
Matrix
Output
Figure 1: Simplified Block Diagram (does not show programming circuit)
CEO
OE
DATA
X3185
December 10, 1997 (Version 1.1)
5-1







XC1701 pdf, 数据表
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs
AC Characteristics Over Operating Condition
CE
RESET/OE
CLK
DATA
9 TSCE
TOE
2 TCE
TLC
7
1
3
TCAC
8 THC
4
TOH
9
TSCE
10
THCE
11 THOE
6 TCYC
5 TDF
4 TOH
X2634
Symbol
Description
XC1701
Min Max
1 TOE
2 TCE
3 TCAC
4 TOH
5 TDF
6 TCYC
7 TLC
8 THC
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold From CE, OE, or CLK
CE or OE to Data Float Delay2
Clock Periods
CLK Low Time3
CLK High Time3
25
45
45
0
50
67
20
20
9 TSCE CE Setup Time to CLK (to guarantee proper counting) 20
10 THCE
CE Hold Time to CLK (to guarantee proper counting)
0
11 THOE
OE Hold Time (guarantees counters are reset)
20
Notes: 1. AC test load = 50 pF
2. Float delays are measured with minimum tester ac load and maximum dc load.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.
XC1701L
XC17512L
Min Max
30
60
60
0
50
100
25
25
25
0
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5-8 December 10, 1997 (Version 1.1)














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