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PDF ( 数据手册 , 数据表 ) XC161CJ

零件编号 XC161CJ
描述 16-Bit Single-Chip Microcontroller
制造商 Infineon Technologies AG
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XC161CJ 数据手册, 描述, 功能
Data Sheet, V2.2, Jun. 2003
XC161CJ
16-Bit Single-Chip Microcontroller
Microcontrollers
Never stop thinking.







XC161CJ pdf, 数据表
XC161
Derivatives
General Device Information
2 General Device Information
2.1 Introduction
The XC161 derivatives are high-performance members of the Infineon XC166 Family of
full featured single-chip CMOS microcontrollers. These devices extend the functionality
and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and
speed. They combine high CPU performance (up to 40 million instructions per second)
with high peripheral functionality and enhanced IO-capabilities. They also provide clock
generation via PLL and various on-chip memory modules such as program Flash,
program RAM, and data RAM.
VAREF
VDDI/P
VAGND
VSSI/P
XTAL1
XTAL2
XTAL3
XTAL4
NMI
RSTIN
RSTOUT
EA
Port 20
6 bit
READY
ALE
RD
WR/WRL
Port 5
12 bit
XC161
PORT0
16 bit
PORT1
16 bit
Port 2
8 bit
Port 3
15 bit
Port 4
8 bit
Port 6
8 bit
Port 7
4 bit
Port 9
6 bit
Figure 1
Logic Symbol
TRST JTAG Debug
5 bit 2 bit
Data Sheet
4 V2.2, 2003-06







XC161CJ equivalent, schematic
XC161
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Input Function
Num. Outp.
P20 IO Port 20 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output. The input threshold of Port 20 is selectable
(standard or special).
The following Port 20 pins also serve for alternate functions:
P20.0 90
O
RD
External Memory Read Strobe, activated for
every external instruction or data read access.
P20.1 91
O
WR/WRL External Memory Write Strobe.
In WR-mode this pin is activated for every
external data write access.
In WRL-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus.
P20.2 92
I
READY READY Input. When the READY function is
enabled, memory cycle time waitstates can be
forced via this pin during an external access.
P20.4 93
O
ALE
Address Latch Enable Output.
Can be used for latching the address into
external memory or an address latch in the
multiplexed bus modes.
P20.5 94
I
EA
External Access Enable pin.
A low level at this pin during and after Reset
forces the XC161 to latch the configuration from
PORT0 and pin RD, and to begin instruction
execution out of external memory.
A high level forces the XC161 to latch the
configuration from pins RD, ALE, and WR, and
to begin instruction execution out of the internal
program memory. "ROMless" versions must
have this pin tied to ‘0’.
P20.12 3
O RSTOUT Internal Reset Indication Output.
Is activated asynchronously with an external
hardware reset. It may also be activated
(selectable) synchronously with an internal
software or watchdog reset.
Is deactivated upon the execution of the EINIT
instruction, optionally at the end of reset, or at
any time (before EINIT) via user software.
Note: Port 20 pins may input configuration values (see EA).
Data Sheet
12 V2.2, 2003-06










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