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PDF ( 数据手册 , 数据表 ) X9279

零件编号 X9279
描述 Single Digitally-Controlled (XDCP) Potentiometer
制造商 Xicor
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X9279 数据手册, 描述, 功能
APPLICATION NOTES AND DEVELOPMENT SYSTEM
AVAILABLE
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Single Supply / Low Power / 256-tap / 2-Wire Bus
X9279
Single Digitally-Controlled (XDCPTM) Potentiometer
FEATURES
• 256 Resistor Taps
• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer
• Wiper Resistance, 100typical @ 5V
• 16 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power Up.
• Standby Current < 5µA Max
• VCC: 2.7V to 5.5V Operation
• 50K, 100Kversions of End to End Resistance
• Endurance: 100,000 Data Changes per Bit per
Register
• 100 yr. Data Retention
• 14-Lead TSSOP, 16-Lead CSP (Chip Scale
Package)
• Low Power CMOS
DESCRIPTION
The X9279 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-Wire
bus interface. The potentiometer has associated with it
a volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC
2-Wire
Bus
Interface
Address
Data
Status
Bus
Interface
and Control
Write
Read
Transfer
Inc/Dec
Control
Power On Recall
Wiper Counter
Register (WCR)
Data Registers
16 Bytes
RH
wiper
50Kand 100K
256-taps
POT
VSS
RW RL
REV 1.1.7 2/6/03
www.xicor.com
Characteristics subject to change without notice. 1 of 24







X9279 pdf, 数据表
X9279
Register Selection (R0 to R3) Table
Register
RB RA Selection
Operations
00
0 Data Register Read and Write;
Wiper Counter Register
Operations
01
1 Data Register Read and Write;
Wiper Counter Register
Operations
10
2 Data Register Read and Write;
Wiper Counter Register
Operations
11
3 Data Register Read and Write;
Wiper Counter Register
Operations
Register Bank Selection (Bank 0 to Bank 3) Table
Bank
P1 P0 Selection
Operations
00
0 Data Register Read and Write;
Wiper Counter Register
Operations
01
1 Data Register Read and Write
Only
10
2 Data Register Read and Write
Only
11
3 Data Register Read and Write
Only
Table 1. Identification Byte Format
Device Type
Identifier
ID3
0
(MSB)
ID2
1
ID1
0
Set to 0
Internal Slave
for proper operation
Address
ID0 0
1
A2 A1 A0
(LSB)
Table 2. Instruction Byte Format
Instruction Opcode
I3 I2 I1 I0
(MSB)
Register
Selection
P1 and P0 are used also for register Bank Selection
for 2-Wire Register Write and Read operations
Register Selection
RB RA P1 P0
Register Selected
DR0
RB
0
(LSB)
DR1
0
DR2
1
Pot Selection (Bank Selection)
Set to P0=0 for potentiometer operations
DR3
1
RA
0
1
0
1
REV 1.1.7 2/6/03
www.xicor.com
Characteristics subject to change without notice. 8 of 24







X9279 equivalent, schematic
X9279
EQUIVALENT A.C. LOAD CIRCUIT
SDA pin
5V
1533
SDA pin
100pF
3V
867
100pF
SPICE Macromodel
RTOTAL
RH
CL CW
10pF
25pF
RW
RL
CL
10pF
AC TIMING
Symbol
fSCL
tCYC
tHIGH
tLOW
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
tHD:DAT
tR
tF
tAA
tDH
TI
tBUF
tSU:WPA
tHD:WPA
Parameter
Clock Frequency
Clock Cycle Time
Clock High Time
Clock Low Time
Start Setup Time
Start Hold Time
Stop Setup Time
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
Noise Suppression Time Constant at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1 Setup Time
A0, A1 Hold Time
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Min.
2500
600
1300
600
600
600
100
30
0
50
1200
0
0
Max.
400
300
300
0.9
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
Typ.
5
Max.
10
Units
ms
REV 1.1.7 2/6/03
www.xicor.com
Characteristics subject to change without notice. 16 of 24










页数 24 页
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