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PDF ( 数据手册 , 数据表 ) X86C64PI

零件编号 X86C64PI
描述 E2 Micro-Peripheral
制造商 Xicor
LOGO Xicor LOGO 


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X86C64PI 数据手册, 描述, 功能
Preliminary Information
XZ8®6CM6ic4rocontroller Family Compatible
64K X86C64
E2 Micro-Peripheral
8192 x 8 Bit
FEATURES
CONCURRENT READ WRITE
—Dual Plane Architecture
Isolates Read/Write Functions
Between Planes
Allows Continuous Execution of Code
From One Plane While Writing in the Other
Plane
Multiplexed Address/Data Bus
—Direct Interface to Popular 8-bit
Microcontrollers, e.g. Zilog Z8 Family
High Performance CMOS
—Fast Access Time, 120 ns
—Low Power
60 mA Maximum Active
200 µA Maximum Standby
Software Data Protection
Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
Toggle Bit
—Early End of Write Detection
Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
DESCRIPTION
The X86C64 is an 8K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X86C64 features a Multiplexed Address and
Data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
The X86C64 is internally configured as two indepen-
dent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an aux-
iliary memory device for code storage.
To write to the X86C64, a three byte command
sequence must precede the byte(s) being written. The
X86C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight, 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the
memory to have varying degrees of alterability in nor-
mal system operation.
FUNCTIONAL DIAGRAM
CE
R/W
DS
SEL
A8–A11
AS
CONTROL
LOGIC
LX
AD
TE
CC
HO
ED
SE
WC
A12
SOFTWARE
DATA
PROTECT
A12
1K BYTES A12 1K BYTES
M
1K BYTES
1K BYTES
U
1K BYTES X 1K BYTES
1K BYTES
1K BYTES
Y DECODE
Z8® is a registered trademark of Zilog Corporation
CONCURRENT READ WRITEis a trademark of Xicor, Inc.
© Xicor, 1991 Patents Pending
3819-2.1 7/29/96 T0/C1/D1 SH
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
3819 FHD F02
1 Characteristics subject to change without notice







X86C64PI pdf, 数据表
X86C64
A.C. CONDITIONS OF TEST
Input Pulse Levels
Input Rise and
Fall Times
Input and Output
Timing Levels
0V to 3.0V
10ns
1.5V
3819 PGM T07
EQUIVALENT A.C. TEST CIRCUIT
5.0V
1923
Output
1370
100pF
3819 FHD F04
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
DS Controlled Read Cycle
Symbol
Parameter
Min.
Max.
Units
PWASL
tAS
tAH
tACC
tDHR
tCS
PWDSH
tDSS
tDSH
tRWS
tHZ(3)
tLZ(3)
Address Strobe Pulse Width
Address Setup Time
Address Hold Time
Data Access Time
Data Hold Time
CE Setup Time
DS Pulse Width
DS Setup Time
DS Hold Time
R/W Setup Time
DS High to High Z Output
DS Low to Low Z Output
DS Controlled Read Cycle
80
20
30
120
0
7
150
30
20
20
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3819 PGM T09
CE
AS
A/D0–A/D7
PWASL
tAS
tCS
tDSS
tAH
AIN
A8–A12
R/W
A8–A12
tRWS
DS
tDSH
tDSH
tACC
DOUT
tDHR
tHZ
tDSH
PWDSH
Note: (3) This parameter is periodically sampled and not 100% tested.
8
3819 FHD F05














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