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PDF ( 数据手册 , 数据表 ) X84256S16I-1.8

零件编号 X84256S16I-1.8
描述 UPort Saver EEPROM
制造商 Xicor
LOGO Xicor LOGO 


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X84256S16I-1.8 数据手册, 描述, 功能
Preliminary
256K
X84256
µPort Saver EEPROM
MPSEEPROM
FEATURES
• Up to 10MHz data transfer rate
• 25ns Read Access Time
• Direct Interface to Microprocessors and
Microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low Power CMOS
—2.5V–5.5V and 5V ±10% Versions
—Standby Current Less than 1µA
—Active Current Less than 3mA
• Byte or Page Write Capable
—64-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 2ms
• High Reliability
—1,000,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Packages Options
—8, 16-Lead SOIC Packages
—14-Lead TSSOP Packages
—8-Lead XBGA Packages
DESCRIPTION
The µPort Saver memories need no serial ports or spe-
cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the µPort Saver uses
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the µPort Saver provides all
the serial benefits, such as low cost, low power, low volt-
age, and small package size while releasing I/Os for
more important uses.
The µPort Saver memory outputs data within 25ns of an
active read signal. This is less than the read access time
of most hosts and provides “no-wait-state” operation.
This prevents bottlenecks on the bus. With rates to 10
MHz, the µPort Saver supplies data faster than required
by most host read cycle specifications. This eliminates
the need for software NOPs.
The µPort Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This “bit serial” interface allows the
µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten-
tion is greater than 100 years.
BLOCK DIAGRAM
System Connection
Ports
Saved
µP
µC
DSP
ASIC
RISC
P0/CS
P1/CLK
P2/DI
P3/DO
A15
A0
D7
D0
OE
WE
Internal Block Diagram
MPS
WP H.V. GENERATION
TIMING & CONTROL
CE
COMMAND
I/O DECODE
OE
AND
CONTROL
LOGIC
WE
X
DEC
EEPROM
ARRAY
32K x 8
Y DECODE
DATA REGISTER
©Xicor, Inc. 1998 Patents Pending
4005 1 8/24/99 WW
1 Characteristics subject to change without notice







X84256S16I-1.8 pdf, 数据表
X84256
Preliminary
A.C. CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits – X84256
VCC = 5V±10% VCC = 2.5V – 5.5V VCC = 1.8V – 3.6V
Symbol
Parameter
Min. Max Min. Max. Min. Max. Units
tRC Read Cycle Time
100 200 330 ns
tCE CE Access Time
25 50
70 ns
tOE OE Access Time
25 50
70 ns
tOEL
OE Pulse Width
50 60
90 ns
tOEH
OE High Recovery Time
50
60
90 ns
tLOW
CE LOW Time
50 70
90 ns
tHIGH
CE HIGH Time
50 120 180 ns
tLZ(4)
CE LOW to Output In Low Z
0
0
0 ns
tHZ(4)
CE HIGH to Output In High Z
0 25 0 30 0 35 ns
tOLZ(4)
OE LOW to Output In Low Z
0
0
0 ns
tOHZ(4) OE HIGH to Output In High Z
0 25 0 30 0 35 ns
tOH
Output Hold from CE or OE HIGH
0
0
0 ns
tWES
WE HIGH Setup Time
25
25
25 ns
tWEH
WE HIGH Hold Time
25 25
25 ns
Notes: (4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes HIGH (whichever occurs
first) to the time when I/O is no longer being driven into a 5pF load.
tRC
tLOW
tHIGH
tCE
CE
WE
OE
I/O
tWES
t OEL
tOE
DATA
t OLZ
t LZ
tOH
t OEH
tWEH
t OHZ
t HZ
HIGH Z
8














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