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PDF ( 数据手册 , 数据表 ) ZL10313

零件编号 ZL10313
描述 Satellite Demodulator
制造商 Zarlink Semiconductor Inc
LOGO Zarlink Semiconductor Inc LOGO 


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ZL10313 数据手册, 描述, 功能
ZL10313
Satellite Demodulator
Data Sheet
Features
• Conforms to EBU specification for DVB-S and
DirecTV specification for DSS
• On-chip digital filtering supports 1 - 45 MSps
symbol rates
• On-chip 60 or 90 MHz dual-ADC
• High speed scanning mode for blind symbol
rate/code rate acquisition
• Automatic spectral inversion resolution
• High level software interface for minimum
development time
• Up to ±22.5 MHz LNB frequency tracking
• DiSEqC™ v2.2: receive/transmit for full control of
LNB, dish and other components
• Compact 64-pin LQFP package (7 x 7 mm)
• A full DVB-S front-end reference design is
available, ref. ZLE10538
Applications
• DVB 1 - 45 MSps compliant satellite receivers
• DSS 20 MSps compliant satellite receivers
• SMATV (Single Master Antenna TV) trans-
modulators
• Satellite PC applications
November 2004
Ordering Information
ZL10313QCG
ZL10313QCG1
ZL10313UBH
64 Pin LQFP Trays, Bake & Drypack
64 Pin LQFP* Trays, Bake & Drypack
Die supplied in wafer form**
*Pb Free Matte Tin
**Please contact Sales for further details
0°C to +70°C
Description
The ZL10313 is a QPSK/BPSK 1 - 45 MSps
demodulator and channel decoder for digital satellite
television transmissions to the European Broadcast
Union ETS 300 421 specification. It receives analogue
I and Q signals from the tuner, digitises and digitally
demodulates this signal, implements the complete
DVB/DSS FEC (Forward Error Correction) and de-
scrambling function. The output is in the form of
MPEG2 or DSS transport stream data packets. The
ZL10313 also provides automatic gain control to the RF
front-end device.
The ZL10313 has a serial 2-wire bus interface to the
control microprocessor. Minimal software is required to
control the ZL10313 because of the built in automatic
search and decode control functions.
I I/P
Q I/P
Dual ADC
De-rotator
Decimation
Filtering
Timing recovery
Matched filter
Phase recovery
DVB
DSS
FEC
MPEG/
DSS
Packets
Analog
AGC
Control
Clock Generation
Acquisition
Control
2-Wire Bus Bus I/O
Interface
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.







ZL10313 pdf, 数据表
ZL10313
Data Sheet
2.0 Functional Overview
2.1 Introduction
ZL10313 is a single-chip variable rate digital QPSK/BPSK satellite demodulator and channel decoder. The
ZL10313 accepts base-band in-phase and quadrature analogue signals and delivers an MPEG or DSS packet data
stream. Digital filtering in ZL10313 removes the need for programmable external anti-alias filtering for all symbol
rates from 1 - 45 MSps. Frequency, timing and carrier phase recovery are all digital and the only feed-back to the
analogue front-end is for automatic gain control. The digital phase recovery loop enables very fine bandwidth
control that is needed to overcome performance degradation due to phase and thermal noise.
All acquisition algorithms are built into the ZL10313 controller. The ZL10313 can be operated in a Command Driven
Control (CDC) mode by specifying the symbol rate and Viterbi code rate. There is also a provision for a search for
unknown symbol rates and Viterbi code rates.
2.2 Analogue-to-Digital Converter
The A/D converters sample single-ended or differential analogue inputs and consist of a dual ADC and circuitry to
provide improved SiNaD (Signal-Noise and Distortion) and channel matching.
The fixed rate sampling clock is provided on-chip using a programmable PLL needing only a low cost 10 to 16 MHz
crystal. Different crystal frequencies can be combined with different PLL ratios, depending on the maximum symbol
rate, allowing a very flexible approach to clock generation. An external clock signal in the range 4 to 16 MHz can
also be used as the master clock.
2.3 QPSK Demodulator
The demodulator in the ZL10313 consists of signal amplitude offset compensation, frequency offset compensation,
decimation filtering, carrier recovery, symbol recovery and matched filtering. The decimation filters give continuous
operation from 2 Mbps to 90 Mbps allowing one receiver to cover the needs of the consumer market as well as the
single carrier per channel (SCPC) market with the same components without compromising performance, that is,
the channel reception is within 0.5 dB from theory. For a given symbol rate, control algorithms on the chip detect the
number of decimation stages needed and switch them in automatically.
The frequency offset compensation circuitry is capable of tracking out up to ±22.5 MHz frequency offset. This
allows the system to cope with relatively large frequency uncertainties introduced by the Low Noise Block (LNB).
Full control of the LNB is provided by the DiSEqC outputs from the ZL10313. Horizontal/vertical polarization and an
instruction modulated 22 kHz signal are available under register control. All DiSEqC functions are implemented on
the ZL10313. An internal state machine that handles all the demodulator functions controls the signal tracking and
acquisition. Various preset modes are available as well as blind acquisition where the receiver has no prior
knowledge of the received signal. Fast acquisition algorithms have been provided for low symbol rate applications.
Full interactive control of the acquisition function is possible for debug purposes. In the event of a signal fade or a
cycle slip, the QPSK demodulator allows sufficient time for the FEC to reacquire lock, for example, via a phase
rotation in the Viterbi decoder. This is to minimize the loss of signal due to the signal fade. Only if the FEC fails to
re-acquire lock for a long period (which is programmable) the QPSK will try to re-acquire the signal.
The matched filter is a root-raised-cosine filter with either 0.20 or 0.35 roll-off, compliant with DSS and DVB
standards. Although not a part of the DVB standard, ZL10313 allows a roll-off of 0.20 to be used with other DVB
parameters. An AGC signal is provided to control the signal levels in the tuner section of the receiver and ensure
the signal level fed to the ZL10313 is set at an optimal value under all reception conditions.
The ZL10313 provides comprehensive information on the input signal and the state of the various parts of the
device. This information includes signal to noise ratio (SNR), signal level, AGC lock, timing and carrier lock signals.
A maskable interrupt output is available to inform the host controller when events occur.
8
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ZL10313 equivalent, schematic
ZL10313
Data Sheet
3. Set DiS_Mode[2:0] = 4 to command the ZL10313 to encode the data and transmit the message.
4. Reset DiS_Mode[2:0] to either 0 or 1 depending on previous setting of 22 kHz off or on. The data loaded into the
DiSEqC_INSTR register is retained, so that if the same message is to be repeated, stage 1 above can be omit-
ted.
2.6.2 DiSEqC Receiving Messages
The ZL10313 will automatically listen for DiSEqC messages 5 ms after a message has been transmitted. If a return
message is expected, the DiS_Mode[2:0] must be set to zero in order to leave the LNB control signal free for
another DiSEqC transmitter to respond. The sequence of events to receive a message are as follows:
1. Ensure that DiSEqC2/GPP2 pin 2 is an input by setting GPP_CTRL register address-20 bit-5 to zero.
2. Enable interrupts if the IRQ pin 43 is used to interrupt the host processor in DiSEqC2_CTRL1 register 121.
3. Monitor DiS_INT register.
4. If bit-3 = 1 and bit-1 = 0, there has been no message received.
5. If a message has been received, bit-0 will be set. If bit-1 is also set the message is complete. DiS_INT register
bits-7-4 indicate how many bytes have been received.
6. Read the received message from DiS_FIFO register 120 by setting the Inhibit Auto Incrementing (IAI) bit-7 in
RADD, the register address byte and sequentially reading DiS_FIFO for the indicated number of bytes. Each
data byte read requires two 2-wire bus reads. The second or the pair of bytes contains the parity bit and a parity
bit error indicator.
The user may choose to wait for the end of message indication, before reading the message, if it is known that the
message is not greater than eight bytes. However, if the length of message is not known, the message should be
read out of the FIFO by the host as it is being received. Care must be taken to avoid a FIFO buffer overflow.
DiS_INT register bits-7-4 will indicate how many bytes remain in the FIFO.
3.0 Microprocessor Control
3.1 RADD: 2-wire Register Address (W)
RADD is the internal 2-wire bus register address. It is the first byte written after the ZL10313 2-wire bus address
when in write mode.
To write to the chip, the bus master should send a START condition and the chip address with the write bit set,
followed by the register address where subsequent data bytes are to be written. Finally, when the 'message' has
been sent, a STOP condition is sent to free the bus.
To read from the chip from register address zero, the bus master should send a START condition and the chip
address with the read bit set, followed by the requisite number of clocks to read the bytes out. Finally a STOP
condition is sent to free the bus. RADD is not sent in this case.
To read from the chip from an address other than zero, the bus master should send the chip address with the write
bit set, followed by the register address from where subsequent data bytes are to be read. Then the bus master
should send a repeat START condition and the chip address with the read bit set, followed by the requisite number
of CLK1 clocks to read the required bytes out. Finally a STOP condition is sent to free the bus. A STOP condition
resets the RADD value to 00.
16
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