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PDF ( 数据手册 , 数据表 ) Z80185

零件编号 Z80185
描述 SMART PERIPHERAL CONTROLLERS
制造商 Zilog.
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Z80185 数据手册, 描述, 功能
Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
PRELIMINARY PRODUCT SPECIFICATION
FEATURES
Part
Z80185
Z80195
ROM
(KB)
32 x 8
0
UART
Baud Rate
512 Kbps
512 Kbps
s 100-Pin QFP Package
s 5.0-Volt Operating Range
s Low-Power Consumption
s 0°C to +70°C Temperature Range
Speed
(MHz)
20, 33
20, 33
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
s Enhanced Z8S180 MPU
s Four Z80 CTC Channels
s One Channel ESCCController
s Two 8-Bit Parallel I/O Ports
s Bidirectional Centronics Interface (IEEE 1284)
s Low-EMI Option
GENERAL DESCRIPTION
The Z80185 and Z80195 are smart peripheral controller
devices designed for general data communications appli-
cations, and architected specifically to accommodate all
input and output (I/O) requirements for serial and parallel
connectivity. Combining a high-performance CPU core
with a variety of system and I/O resources, the Z80185/195
are useful in a broad range of applications. The Z80195 is
the ROMless version of the device.
The Z80185 and Z80195 feature an enhanced Z8S180
microprocessor linked with one enhanced channel of the
Z85230 ESCCserial communications controller, and 25
bits of parallel I/O, allowing software code compatibility
with existing software code.
Seventeen lines can be configured as bidirectional
Centronics (IEEE 1284) controllers. When configured as a
1284 controller, an I/O line can operate in either the host or
peripheral role in compatible, nibble, byte or ECP mode. In
addition, the Z80185 includes 32 Kbytes of on-chip ROM.
These devices are well-suited for external modems using
a parallel interface, protocol translators, and cost-effective
WAN adapters. The Z80185/195 is ideal for handling all
laser printer I/O, as well as the main processor in cost-
effective printer applications.
Notes:
All Signals with a preceding front slash, "/", are active Low.
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
V
CC
GND
V
DD
VSS
DS971850301
1







Z80185 pdf, 数据表
Zilog
0
Address
T1
/IROQ
/RD
/WR
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
I/O Read Cycle
T2 TW T3
I/O Write Cycle
T1 T2 TW T3
28 29 28
29
9 13
22
25
Figure 6. CPU Timing
Ø
TOUT//DREQ
(At level
sense)
TOUT//DREQ
(At edge
sence)
ST
CPU or DMA Read/Write Cycle
T1 T2 Tw
45
46 [1]
45
45 [2]
[3]
17
DMA Control Signals
[1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3.
[2] tDRQS and tDRQH are specified for the rising edge of clock.
[3] DMA cycle starts.
[4] CPU cycle starts.
Figure 7. DMA Control Signals
T3
T1
18
[4]
8 DS971850301







Z80185 equivalent, schematic
Zilog
PRELIMINARY
I/O Port Timing
No. Symbol
Parameter
Z80185 / Z80195
(20 MHz)
Min Max
A1 TdWR (PIA) Data Valid Delay from WR Rise
60
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Z80185 / Z80195
(33 MHz)
Min Max Units
60 ns
External Bus Master Timing
No. Symbol
B1 TsA(wf)
(rf)
B2 TsIO(wf)
(rf)
B3 Th
B4 TdRD(DO)
B5 TdRIr(DOz)
B6 TsDI(WRf)
B7 TsA(IORQf)
B8 TsA(RDf)
B9 TsA(WRf)
Parameter
Address Valid to WR or
RD Fall Time
IORQ Fall to WR or
RD Fall Time
Data Hold Time (from WR Rise)
RD Fall to Data Out Delay
RD,IORQ Rise to Data Float Time
Data In to WR Fall Setup Time
Address to IORQ Fall Setup Time
Address to RD Fall Setup Time
Address to WR Fall Setup Time
Z80185 / Z80195
(20 MHz)
Min Max
Z80185 / Z80195
(33 MHz)
Min Max Units
40 40 ns
20 20 ns
5 5 ns
35 35 ns
5 5 ns
20 20 ns
20 20 ns
40 40 ns
40 40 ns
16 DS971850301










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