|
|
零件编号 | Z8018033FEC | ||
描述 | ENHANCED Z180 MICROPROCESSOR | ||
制造商 | Zilog. | ||
LOGO | |||
1 Page
Z8018x
Family MPU
User Manual
UM005001-ZMP0400
ZiLOG WORLDWIDE HEADQUARTERS •910 E. HAMILTON AVENUE •CAMPBELL, CA 95008
TELEPHONE: 408.558.8500 •FAX: 408.558.8300 •WWW.ZILOG.COM
Z8018x Family
MPU User Manual
ix
List of Figures
Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Figure 1. 64-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 2. 68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. 80-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. Z80180/Z8S180/Z8L180 Block Diagram . . . . . . . . . . . . . . .6
Figure 5. Operation Mode Control Register . . . . . . . . . . . . . . . . . . . .15
Figure 6. M1 Temporary Enable Timing . . . . . . . . . . . . . . . . . . . . . .16
Figure 7. I/O Read and Write Cycles with IOC = 1
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 8. I/O Read and Write cycles with IOC = 0
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 9. Op Code Fetch (without Wait State) Timing Diagram . . . .19
Figure 10. Op Code Fetch (with Wait State) Timing Diagram . . . . . .20
Figure 11. Memory Read/Write (without Wait State)
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 12. Memory Read/Write (with Wait State)
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 13. I/O Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . .23
Figure 14. Instruction Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 15. RESET Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 16. Bus Exchange Timing During Memory Read . . . . . . . . . . .26
Figure 17. Bus Exchange Timing During CPU Internal Operation . . .27
Figure 18. WAIT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 19. Memory and I/O Wait State Insertion
(DCNTL – DMA/Wait Control Register) . . . . . . . . . . . . . .29
Figure 20. HALT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .33
UM005001-ZMP0400
Z 8018x Fam ily
M PU Us e r M anual
1
Z80180, Z8S180, Z8L180 MPU Operation
FEATURES
• Operating Frequency to 33 MHz
• On-Chip MMU Supports Extended Address Space
• Two DMA Channels
• On-Chip Wait State Generators
• Two Universal Asynchronous Receiver/Transmitter (UART) Channels
• Two 16-Bit Timer Channels
• On-Chip Interrupt Controller
• On-Chip Clock Oscillator/Generator
• Clocked Serial I/O Port
• Code Compatible with ZiLOG Z80 CPU
• Extended Instructions
GENERAL DESCRIPTION
Based on a microcoded execution unit and an advanced CMOS
manufacturing technology, the Z80180, Z8S180, Z8L180 (Z8X180) is an
8-bit MPU which provides the benefits of reduced system costs and low
power operation while offering higher performance and maintaining
compatibility with a large base of industry standard software written
around the ZiLOG Z8X CPU.
Higher performance is obtained by virtue of higher operating frequencies,
reduced instruction execution times, an enhanced instruction set, and an
UM005001-ZMP0400
|
|||
页数 | 70 页 | ||
下载 | [ Z8018033FEC.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
Z8018033FEC | ENHANCED Z180 MICROPROCESSOR | Zilog. |
零件编号 | 描述 | 制造商 |
STK15C88 | 256-Kbit (32 K x 8) PowerStore nvSRAM | Cypress Semiconductor |
NJM4556 | DUAL HIGH CURRENT OPERATIONAL AMPLIFIER | New Japan Radio |
EL1118-G | 5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLER | Everlight |
DataSheet8.cn | 2020 | 联系我们 | 搜索 | Simemap |