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PDF ( 数据手册 , 数据表 ) XQ18V04VQ44N

零件编号 XQ18V04VQ44N
描述 QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
制造商 Xilinx
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XQ18V04VQ44N 数据手册, 描述, 功能
0
R
DS082 (v1.2) November 5, 2001
05
Features
• In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
- Endurance of 2,000 program/erase cycles
- Program/erase over full military temperature range
• IEEE Std 1149.1 boundary-scan (JTAG) support
• Cascadable for storing longer or multiple bitstreams
• Dual configuration modes
- Serial Slow/Fast configuration (up to 33 MHz)
- Parallel (up to 264 Mbps at 33 MHz)
• Low-power advanced CMOS FLASH process
• 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals.
• 3.3V or 2.5V output capability
• Available in CC44 and VQ44 packages.
• Design support using the Xilinx Alliance™ and
Foundation™ series software packages.
• JTAG command initiation of standard FPGA
configuration.
• Available to Standard Microcircuit Drawing
5962-01525.
- For more information contact Defense Supply
Center Columbus (DSCC) at
http://www.dscc.dla.mil
CLK CE
QPro XQ18V04 (XQR18V04) QML
In-System Programmable
Configuration PROMs
Preliminary Product Specification
Radiation Hardenned XQR18V04
• Fabricated on Epitaxial Substrate
• Latch-Up Immune to >120 LET
• Guaranteed TID of 40 kRad(Si)
• Supports SEU Scrubbing
Description
Xilinx introduces the QPro™ XQ18V04 and XQR18V04
series of QML in-system programmable and radiation hard-
ened configuration PROMs. Initial devices in this 3.3V fam-
ily are a 4-megabit PROM that provide an easy-to-use,
cost-effective method for re-programming and storing large
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising CCLK, data is available on the PROM
DATA (D0) pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. When the FPGA is in Slave
Serial mode, the PROM and the FPGA are clocked by an
external clock.
When the FPGA is in Express or SelectMAP Mode, an
external oscillator will generate the configuration clock that
drives the PROM and the FPGA. After the rising CCLK
edge, data are available on the PROMs DATA (D0-D7) pins.
The data will be clocked into the FPGA on the following ris-
ing edge of the CCLK. Neither Express nor SelectMAP uti-
lize a Length Count, so a free-running oscillator may be
used. See Figure 6.
OE/Reset
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Address
Memory
Data
Serial
or
Parallel
Interface
CEO
D0 DATA
(Serial or Parallel
[Express/SelectMAP] Mode)
7
D[1:7]
Express Mode and
SelectMAP Interface
CF
Figure 1: XQ18V04 Series Block Diagram
DS026_01_021000
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS082 (v1.2) November 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1







XQ18V04VQ44N pdf, 数据表
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
R
Connecting Configuration PROMs
Connecting the FPGA device with the configuration PROM
(see Figure 6).
The DATA output(s) of the PROM(s) drives the DIN
input of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s) (in Master Serial mode only).
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The OE/RESET input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a VCC glitch.
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of the first FPGA device, provided
that DONE is not permanently grounded. CE can also
be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 20 mA maximum.
Express/SelectMap mode is similar to slave serial
mode. The DATA is clocked out of the PROM one byte
per CCLK instead of one bit per CCLK cycle. See
FPGA data sheets for special configuration
requirements.
Initiating FPGA Configuration
The XQ(R)18V04 devices incorporate a pin named CF that
is controllable through the JTAG CONFIG instruction. Exe-
cuting the CONFIG instruction through JTAG pulses the CF
low for 300-500 ns, which resets the FPGA and initiates
configuration.
The CF pin must be connected to the PROGRAM pin on the
FPGA(s) to use this feature.
The JTAG Programmer software can also issue a JTAG
CONFIG command to initiate FPGA configuration through
the "Load FPGA" setting.
Selecting Configuration Modes
The XQ(R)18V04 accommodates serial and parallel meth-
ods of configuration. The configuration modes are select-
able through a user control register in the XQ(R)18V04
device. This control register is accessible through JTAG,
and is set using the "Parallel mode" setting on the Xilinx
JTAG Programmer software. Serial output is the default pro-
gramming mode.
Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration pro-
gram from an external memory. Xilinx PROMs are designed
to accommodate the Master Serial mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA
mode-select pins are Low (M0=0, M1=0, M2=0). Data is
read from the PROM sequentially on a single data line. Syn-
chronization is provided by the rising edge of the temporary
signal CCLK, which is generated by the FPGA during con-
figuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line, a clock line, and two control
lines are required to configure an FPGA. Data from the
PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK. If the user-programmable,
dual-function DIN pin on the FPGA is used only for configu-
ration, it must still be held at a defined level during normal
operation. The Xilinx FPGA families take care of this auto-
matically with an on-chip pull-up resistor.
Cascading Configuration PROMs
For multiple FPGAs configured as a serial daisy-chain, or a
single FPGA requiring larger configuration memories in a
serial or SelectMAP configuration mode, cascaded PROMs
provide additional memory (Figure 5). Multiple XQ(R)18V04
devices can be concatenated by using the CEO output to
drive the CE input of the downstream device. The clock
inputs and the data outputs of all XQ(R)18V04 devices in
the chain are interconnected. After the last bit from the first
PROM is read, the next clock signal to the PROM asserts its
CEO output Low and drives its DATA line to a high-imped-
ance state. The second PROM recognizes the Low level on
its CE input and enables its DATA output. See Figure 6.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the PROM OE/RESET pin
goes Low.
8
www.xilinx.com
DS082 (v1.2) November 5, 2001
1-800-255-7778
Preliminary Product Specification







XQ18V04VQ44N equivalent, schematic
QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
Ordering Information
R
Device Number
Package Type
XQ18V04 CC44 V
Device Ordering Options
Device Type
XQ18V04
XQR18V04(1)
CC44
VQ44
Package
44-pin Ceramic Chip Carrier Package
44-pin Plastic Thin Quad Flat Package
Notes:
1. Radiation Hardened.
Grade (Manufacturing Flow /
Temperature Range)
Grade
M Military Ceramic TC = 55°C to +125°C
N Military Plastic
V QPro-Plus
TJ = 55°C to +125°C
TC = 55°C to +125°C
Generic Standard
Microcircuit Drawing (SMD)
Radiation Hardened(1)
Device Type
5962 - 01525 Q Y A
Lead Finish
Package Type
QML Certified MIL-PRF-38535
SMD Ordering Options
Device Type
QML
Package
5962-01525 XQ18V04
- 44-pin Ceramic Chip Carrier Package
5962R01525 XQR18V04
- 44-pin Plastic Thin Quad Flat Package
Notes:
1. Type R designates Radiation Hardened.
Valid Ordering Combinations
Mil-Std
XQ18V04CC44M
XQ18V04VQ44N
SMD
-
-
Rad Hard
XQR18V04CC44M
XQR18V04CC44V
Lead Finish
Solder Dip
Solder Plate
SMD
-
16
www.xilinx.com
DS082 (v1.2) November 5, 2001
1-800-255-7778
Preliminary Product Specification










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