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PDF ( 数据手册 , 数据表 ) K9F2808U0C-DCB0

零件编号 K9F2808U0C-DCB0
描述 16M x 8 Bit / 8M x 16 Bit NAND Flash Memory
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


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K9F2808U0C-DCB0 数据手册, 描述, 功能
K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0
K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0
FLASH MEMORY
Document Title
16M x 8 Bit , 8M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 Initial issue.
1.0 TBGA PKG Dimension Change
48-Ball, 6.0mm x 8.5mm --> 63-Ball, 9.0mm x 11.0mm
2.0 1.A3 Pin assignment of TBGA Package is changed.(Page 4)
(before) NC --> (after) Vss
2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 32)
3. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 33)
2.1 The min. Vcc value 1.8V devices is changed.
K9F28XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V
Draft Date
Apr. 15th 2002
Sep. 5th 2002
Dec.10th 2002
Mar. 6th 2003
Pb-free Package is added.
2.2
K9F2808U0C-FCB0,FIB0
K9F2808Q0C-HCB0,HIB0
K9F2816U0C-HCB0,HIB0
K9F2816U0C-PCB0,PIB0
K9F2816Q0C-HCB0,HIB0
K9F2808U0C-HCB0,HIB0
K9F2808U0C-PCB0,PIB0
Mar. 13rd 2003
Some AC parameter is changed(K9F28XXQ0C).
2.3
tWC tWH tWP tRC tREH tRP tREA tCEA
Before 45 15 25 50 15 25 30 45
After 60 20 40 60 20 40 40 55
Mar. 26th 2003
2.4 New definition of the number of invalid blocks is added.
May. 24th 2003
(Minimum 502 valid blocks are guaranteed for each contiguous 64Mb
memory space)
Remark
Advance
Advance
Preliminary
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1







K9F2808U0C-DCB0 pdf, 数据表
K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0
K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0
FLASH MEMORY
Figure 1-2. K9F2816X0C (X16) FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
A9 - A23
A0 - A7
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
128M + 4M Bit
NAND Flash
ARRAY
(256 + 8)Word x 32768
Command
Command
Register
Page Register & S/A
Y-Gating
I/O Buffers & Latches
CE Control Logic
RE & High Voltage
WE Generator
Global Buffers
Output
Driver
VCC/VCCQ
VSS
I/0 0
I/0 15
CLE ALE WP
Figure 2-2. K9F2816X0C (X16) ARRAY ORGANIZATION
1 Block =32 Pages
= (8K + 256) Word
32K Pages
(=1,024 Blocks)
Page Register
(=256 Words)
256Word
8 Word
1 Page = 264 Word
1 Block = 264 Word x 32 Pages
= (8K + 256) Word
1 Device = 264Words x 32Pages x 1024 Blocks
= 132 Mbits
16 bit
Page Register
256 Word
8 Word
I/O 0 ~ I/O 15
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4
1st Cycle
A0
A1
A2
A3
A4
2nd Cycle A9
A10 A11 A12 A13
3rd Cycle A17 A18 A19 A20 A21
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
I/O 5
A5
A14
A22
I/O 6
A6
A15
A23
I/O 7
A7
A16
L*
I/O8 to 15
L* Column Address
L* Row Address
(Page Address)
L*
8







K9F2808U0C-DCB0 equivalent, schematic
K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-VCB0,VIB0
K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0
FLASH MEMORY
Pointer Operation of K9F2808X0C(X8)
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’area(0~255byte), ’01h’command sets the pointer to ’B’area(256~511byte), and ’50h’command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’or ’50h’is sustained until another address pointer command is inputted. ’01h’command, however, is effec-
tive only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’command,
the address pointer returns to ’A’area by itself. To program data starting from ’A’or ’C’area, ’00h’or ’50h’command must be input-
ted before ’80h’command is written. A complete read operation prior to ’80h’command is not necessary. To program data starting
from ’B’area, ’01h’command must be inputted right before ’80h’command is written.
Table 2. Destination of the pointer
Command
00h
01h
50h
Pointer position
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
Area
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
(00h plane)
"B" area
"C" area
(01h plane) (50h plane)
256 Byte
256 Byte
16 Byte
"A" "B" "C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 4. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’area
The address pointer is set to ’A’area(0~255), and sustained
Address / Data input
00h 80h
10h 00h
Address / Data input
80h 10h
’A’,’B’,’C’area can be programmed.
It depends on how many data are inputted.
’00h’command can be omitted.
(2) Command input sequence for programming ’B’area
The address pointer is set to ’B’area(256~512), and will be reset to
’A’area after every program operation is executed.
Address / Data input
Address / Data input
01h 80h
10h 01h 80h 10h
’B’, ’C’area can be programmed.
It depends on how many data are inputted.
’01h’command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’area
The address pointer is set to ’C’area(512~527), and sustained
Address / Data input
Address / Data input
50h 80h
10h 50h 80h 10h
Only ’C’area can be programmed.
’50h’command can be omitted.
16










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