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PDF ( 数据手册 , 数据表 ) K9F2808U0A-YCB0

零件编号 K9F2808U0A-YCB0
描述 16M x 8 Bit NAND Flash Memory
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


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K9F2808U0A-YCB0 数据手册, 描述, 功能
K9F2808U0A-YCB0, K9F2808U0A-YIB0
Document Title
16M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No. History
0.0 Initial issue.
Draft Date
April 10th 1999
0.1 1. Revised real-time map-out algorithm(refer to technical notes)
July 23th 1999
0.2 1. Changed device name
- KM29U128AT -> K9F2808U0A-YCB0
- KM29U128AIT -> K9F2808U0A-YIB0
Sep. 15th 1999
0.3 1. Changed sequential row read opera tion
Mar. 21th 2000
- The Sequential Read 1 and 2 operation is allowed only within a block
2. Changed invalid block(s) marking method prior to shipping
- The invalid block(s) information is written the 1st or 2nd page of the
invalid block(s) with 00h data
--->The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has 00h data at the column address of 517.
0.4 1. Changed endurance : 1million -> 100K program/erase cycles
May 15th 2000
2. Changed invalid block(s) marking method prior to shipping
- The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has 00h data at the column address of 517.
--->The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has non-FFh data at the column address of 517.
0.5 1. Changed SE pin description
July 17th 2000
- SE is recommended to coupled to GND or Vcc and should not be
toggled during reading or programming.
0.6 1. Changed don’t care mode in address cycles
Nov. 20th 2000
- *X can be "High" or "Low" => *L must be set to "Low"
2. Explain how pointer operation works in detail.
3. Renamed GND input (pin # 6) on behalf of SE (pin # 6)
- The SE input controls the access of the spare area. When SE is high,
the spare area is not accessible for reading or programming. SE is rec
ommended to be coupled to GND or Vcc and should not be toggled
during reading or programming.
=> Connect this input pin to GND or set to static low state unless the
sequential read mode excluding spare area is used.
4. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes into
Busy for maximum 5us.
Remark
Advanced
Information
Preliminary
Preliminary
Final
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1







K9F2808U0A-YCB0 pdf, 数据表
K9F2808U0A-YCB0, K9F2808U0A-YIB0
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
CLE Set-up Time
tCLS
0
CLE Hold Time
tCLH
10
CE Setup Time
tCS 0
CE Hold Time
tCH 10
WE Pulse Width
tWP 25
ALE Setup Time
tALS
0
ALE Hold Time
Data Setup Time
tALH
tDS
10
20
Data Hold Time
tDH 10
Write Cycle Time
tWC 50
WE High Hold Time
tWH 15
Max
-
-
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE Delay( ID read )
ALE to RE Delay(Read cycle)
CE to RE Delay( ID read)
Ready to RE Low
RE Pulse Width
WE High to Busy
Read Cycle Time
RE Access Time
RE High to Output Hi-Z
CE High to Output Hi-Z
RE High Hold Time
Output Hi-Z to RE Low
Last RE High to Busy(at sequential read)
CE High to Ready(in case of interception by CE at read)
CE High Hold Time(at the last serial read)(2)
RE Low to Status Output
CE Low to Status Output
WE High to RE Low
RE access time(Read ID)
Device Resetting Time(Read/Program/Erase)
Symbol
tR
tAR1
tAR2
tCR
tRR
tRP
tWB
tRC
tREA
tRHZ
tCHZ
tREH
tIR
tRB
tCRY
tCEH
tRSTO
tCSTO
tWHR
tREADID
tRST
Min
-
100
50
100
20
30
-
50
-
15
-
15
0
-
-
100
-
-
60
-
-
NOTE :
1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
Max
10
-
-
-
-
-
100
-
35
30
20
-
-
100
50 +tr(R/B)(1)
-
35
45
-
35
5/10/500(3)
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
8







K9F2808U0A-YCB0 equivalent, schematic
K9F2808U0A-YCB0, K9F2808U0A-YIB0
* Status Read Cycle
FLASH MEMORY
CLE
CE
WE
RE
I/O0~7
tCLS
tCS
tCLH
tCLS
tCH
tWP
tWHR
tCSTO
tCHZ*
tDS tDH
70h
tIR tRSTO
tRHZ*
Status Output
READ1 OPERATION(READ ONE PAGE)
CLE
CE
WE
ALE
RE
I/O0~7
R/B
tWC
tWB
tAR2
tR tRC
tRR
00h or 01h A0 ~ A7 A9 ~ A16 A17 ~ A23
Column Page(Row)
Address Address
Busy
Dout N Dout N+1 Dout N+2 Dout N+3
tCEH
tCHZ
tCRY
tRHZ
Dout 527
tRB
16










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