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PDF ( 数据手册 , 数据表 ) K9F1G08U0M-PCB0

零件编号 K9F1G08U0M-PCB0
描述 1Gb Gb 1.8V NAND Flash Errata
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


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K9F1G08U0M-PCB0 数据手册, 描述, 功能
ELECTRONICS
March. 2003
San 16 Banwol-Ri
Taean-Eup Hwasung- City
Kyungki Do, Korea
Tel.) 82 - 31 - 208 - 6463
Fax.) 82 - 31 -208 - 6799
1Gb 1.8V NAND Flash Errata
Description : Some of AC characteristics are not meeting the specification.
> AC characteristics : Refer to Table
Affected Products : K9F1G08Q0M-YCB0/YIB0, K9F1G16Q0M-YCB0/YIB0
K9K2G08Q0M-YCB0/YIB0, K9K2G16Q0M-YCB0/YIB0
Improvement schedule : The components targeted to meet the specification
is scheduled to be available by workweek 25 along
with the final specification values.
Workaround : Relax the relevant timing parameters according to the table.
Table
Parameters
tWC
Specification
45
Relaxed Condition 80
tWH
15
20
tWP
25
60
UNIT : ns
tRC tREH tRP tREA tCEA
50 15 25 30 45
80 20 60 60 75
Sincerely,
Product Planning & Application Eng.
Memory Division
Samsung Electronics Co.
1







K9F1G08U0M-PCB0 pdf, 数据表
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
FLASH MEMORY
Figure 1-1. K9F1G08X0M (X8) Functional Block Diagram
VCC
VSS
A12 - A27
X-Buffers
Latches
& Decoders
1024M + 32M Bit
NAND Flash
ARRAY
A0 - A11
Y-Buffers
Latches
& Decoders
(1024 + 32)Byte x 65536
Data Register & S/A
Command
Command
Register
Cache Register
Y-Gating
I/O Buffers & Latches
CE Control Logic
RE & High Voltage
WE Generator
Global Buffers
Output
Driver
CLE ALE PRE WP
VCC
VSS
I/0 0
I/0 7
Figure 2-1. K9F1G08X0M (X8) Array Organization
1 Block = 64 Pages
(128K + 4k) Byte
64K Pages
(=1,024 Blocks)
2K Bytes
64 Bytes
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 1024 Blocks
= 1056 Mbits
8 bit
Page Register
2K Bytes
I/O 0 ~ I/O 7
64 Bytes
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A8 A9 A10 A11 *L *L *L
3rd Cycle A12 A13 A14 A15 A16 A17 A18
4th Cycle A20 A21 A22 A23 A24 A25 A26
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
I/O 7
A7
*L
A19
A27
Column Address
Column Address
Row Address
Row Address
SAMSUNG
7







K9F1G08U0M-PCB0 equivalent, schematic
K9F1G08U0M-VCB0,VIB0,FCB0,FIB0
K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0
K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Write 60h
Write Block Address
Start
Write 00h
Write Address
Write D0h
Write 30h
Read Status Register
Read Data
I/O 6 = 1 ?
or R/B = 1 ?
No
* No
Erase Error
Yes
I/O 0 = 0 ?
Yes
Erase Completed
ECC Generation
No
Reclaim the Error
Verify ECC
Yes
Page Read Completed
* : If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
{1st
(n-1)th
nth
Block A
an error occurs.
(page)
2
Buffer memory of the controller.
{1st
(n-1)th
nth
(page)
Block B
1
* Step1
When an error happens in the nth page of the Block ’A’during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’by creating an ’invalid Block’table or other appropriate scheme.
SAMSUNG
15










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