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PDF ( 数据手册 , 数据表 ) K9F1208Q0A-XXB0

零件编号 K9F1208Q0A-XXB0
描述 512Mb/256Mb 1.8V NAND Flash Errata
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


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K9F1208Q0A-XXB0 数据手册, 描述, 功能
ELECTRONICS
March. 2003
San 16 Banwol-Ri
Taean-Eup Hwasung- City
Kyungki Do, Korea
Tel.) 82 - 31 - 208 - 6463
Fax.) 82 - 31 -208 - 6799
512Mb/256Mb 1.8V NAND Flash Errata
Description : Some of AC characteristics are not meeting the specification.
> AC characteristics : Refer to Table
Affected Products : K9F1208Q0A-XXB0, K9F1216Q0A-XXB0
K9F5608Q0C-XXB0, K9F5616Q0C-XXB0
K9K1208Q0C-XXB0, K9K1216Q0C-XXB0
Improvement schedule : The components without this restriction will
be available from work week 23 or after.
Workaround : Relax the relevant timing parameters according to the table.
Table
UNIT : ns
Parameters
tWC tWH tWP tRC tREH tRP tREA tCEA
Specification
45 15 25 50 15 25 30 45
Relaxed Condition 80 20 60 80 20 60 60 75
Sincerely,
Product Planning & Application Eng.
Memory Division
Samsung Electronics Co.
1







K9F1208Q0A-XXB0 pdf, 数据表
K9F5608U0C-VCB0,VIB0,FCB0,FIB0
K9F5608Q0C-DCB0,DIB0,HCB0,HIB0
K9F5608U0C-YCB0,YIB0,PCB0,PIB0
K9F5608U0C-DCB0,DIB0,HCB0,HIB0
K9F5616Q0C-DCB0,DIB0,HCB0,HIB0
K9F5616U0C-YCB0,YIB0,PCB0,PIB0
K9F5616U0C-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Figure 1-1. K9F5608X0C (X8) FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
A9 - A24
A0 - A7
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
256M + 8M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 65536
Command
A8
Command
Register
Page Register & S/A
Y-Gating
I/O Buffers & Latches
CE Control Logic
RE & High Voltage
WE Generator
Global Buffers
Output
Driver
VCC/VCCQ
VSS
I/0 0
I/0 7
CLE ALE WP
Figure 2-1. K9F5608X0C (X8) ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Byte
64K Pages
(=2,048 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
512Byte
16 Byte
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 2048 Blocks
= 264 Mbits
8 bit
Page Register
512 Byte
16 Byte
I/O 0 ~ I/O 7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A9
A10 A11 A12 A13 A14 A15
3rd Cycle A17 A18 A19 A20 A21 A22 A23
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* The device ignores any additional input of address cycles than reguired.
I/O 7
A7
A16
A24
Column Address
Row Address
(Page Address)
7







K9F1208Q0A-XXB0 equivalent, schematic
K9F5608U0C-VCB0,VIB0,FCB0,FIB0
K9F5608Q0C-DCB0,DIB0,HCB0,HIB0
K9F5608U0C-YCB0,YIB0,PCB0,PIB0
K9F5608U0C-DCB0,DIB0,HCB0,HIB0
K9F5616Q0C-DCB0,DIB0,HCB0,HIB0
K9F5616U0C-YCB0,YIB0,PCB0,PIB0
K9F5616U0C-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Status Register
Read Data
ECC Generation
I/O 6 = 1 ?
or R/B = 1 ?
No
* No
Erase Error
Yes
I/O 0 = 0 ?
Yes
Erase Completed
No
Reclaim the Error
Verify ECC
Yes
Page Read Completed
* : If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
{1st
(n-1)th
nth
(page)
Block A
an error occurs.
2
Buffer memory of the controller.
{1st
(n-1)th
nth
(page)
Block B
1
* Step1
When an error happens in the nth page of the Block ’A’during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’by creating an ’invalid Block’table or other appropriate scheme.
15










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