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PDF ( 数据手册 , 数据表 ) K9F1208D0B

零件编号 K9F1208D0B
描述 64M x 8 Bit NAND Flash Memory
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


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K9F1208D0B 数据手册, 描述, 功能
KK99FF11220088BR00BB
K9F1208U0B
Document Title
64M x 8 Bit NAND Flash Memory
Preliminary
FLASH MEMORY
Revision History
Revision No. History
0.0 Initial issue.
0.1 1. Note 1 ( Program/Erase Characteristics) is added( page 14 )
2. NAND Flash Technical Notes is changed.
-Invalid block -> initial invalid block ( page 16 )
-Error in write or read operation ( page 17 )
-Program Flow Chart ( page 17 )
3. Vcc range is changed
-2.4V~2.9V -> 2.5V~2.9V
-1.7V~1.95V ->1.65V~1.95V
4. Multi plane operation and Copy-Back Program are not supported with 1.8V
device.
Draft Date
Apr. 24th 2004
Oct. 11th.2004
Remark
Advance
Preliminary
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1







K9F1208D0B pdf, 数据表
KK99FF11220088BR00BB
K9F1208U0B
Preliminary
FLASH MEMORY
Figure 1-1. K9F1208X0B FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
A9 - A25
A0 - A7
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
512M + 16M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 131072
Command
A8
Command
Register
Page Register & S/A
Y-Gating
I/O Buffers & Latches
CE Control Logic
RE & High Voltage
WE Generator
Global Buffers
Output
Driver
VCC/VCCQ
VSS
I/0 0
I/0 7
CLE ALE WP
Figure 2-1. K9F1208X0B ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Byte
128K Pages
(=4,096 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
512Byte
16 Byte
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 4096 Blocks
= 528 Mbits
8 bit
Page Register
512 Byte
16 Byte
I/O 0 ~ I/O 7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A9
A10 A11 A12 A13 A14 A15
3rd Cycle A17 A18 A19 A20 A21 A22 A23
4th Cycle A25
*L
*L
*L
*L
*L
*L
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
I/O 7
A7
A16
A24
*L
Column Address
Row Address
(Page Address)
8







K9F1208D0B equivalent, schematic
KK99FF11220088BR00BB
K9F1208U0B
Preliminary
FLASH MEMORY
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is
placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of
every initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable
in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize
the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following sug-
gested flow chart(Figure 4). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update)
No
Initial Invalid Block(s) Table
* Check "FFh" at the column address
517 of the 1st and 2nd page in the block
Check "FFh" ?
Yes
No Last Block ?
Yes
End
Figure 4. Flow chart to create initial invalid block table.
16










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