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PDF ( 数据手册 , 数据表 ) K9D1G08V0M

零件编号 K9D1G08V0M
描述 64MB & 128MB SmartMediaTM Card
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


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K9D1G08V0M 数据手册, 描述, 功能
K9F1G08Q0M K9F1G16Q0M
K9F1G08D0M K9F1G16D0M
K9F1G08U0M K9F1G16U0M
Document Title
128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No History
0.0 1. Initial issue
Draft Date
July. 5. 2001
Remark
Advance
0.1 1. Iol(R/B) of 1.8V is changed.
- min. value : 7mA --> 3mA
- Typ. value : 8mA --> 4mA
Nov. 5. 2001
2. AC parameter is changed.
tRP(min.) : 30ns --> 25ns
3. A recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences as shown in Figure 17.
---> A recovery time of minimum 10µs is required before internal circuit gets
ready for any command sequences as shown in Figure 17.
Dec. 4. 2001
0.2 1. ALE status fault in ’Random data out in a page’ timing diagram(page 19)
is fixed.
0.3 1. tAR1, tAR2 are merged to tAR.(Page11)
(Before revision) min. tAR1 = 10ns , min. tAR2 = 50ns
(After revision) min. tAR = 10ns
2. min. tCLR is changed from 50ns to 10ns.(Page11)
3. min. tREA is changed from 35ns to 30ns.(Page11)
4. min. tWC is changed from 50ns to 45ns.(Page11)
5. tRHZ is devided into tRHZ and tOH.(Page11)
- tRHZ : RE High to Output Hi-Z
- tOH : RE High to Output Hold
6. tCHZ is devided into tCHZ and tOH.(Page11)
- tCHZ : CE High to Output Hi-Z
- tOH : CE High to Output Hold
Apr. 25. 2002
0.4
1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 35)
Nov. 22.2002
2. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 36)
0.5 1. The min. Vcc value 1.8V devices is changed.
K9F1GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V
Mar. 6.2003
0.6 Pb-free Package is added.
K9F1G08U0M-FCB0,FIB0
K9F1G08Q0M-PCB0,PIB0
K9F1G08U0M-PCB0,PIB0
K9F1G16U0M-PCB0,PIB0
K9F1G16Q0M-PCB0,PIB0
Mar. 13.2003
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
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K9D1G08V0M pdf, 数据表
K9F1G08Q0M K9F1G16Q0M
K9F1G08D0M K9F1G16D0M
K9F1G08U0M K9F1G16U0M
FLASH MEMORY
Figure 1-2. K9F1G16X0M (X16) Functional Block Diagram
VCC
VSS
A11 - A26
X-Buffers
Latches
& Decoders
1024M + 32M Bit
NAND Flash
ARRAY
A0 - A10
Y-Buffers
Latches
& Decoders
Command
Command
Register
(512 + 64)Word x 65536
Data Register & S/A
Cache Register
Y-Gating
I/O Buffers & Latches
CE Control Logic
RE & High Voltage
WE Generator
Global Buffers
Output
Driver
CLE ALE PRE WP
VCC
VSS
I/0 0
I/0 15
Figure 2-2. K9F1G16X0M (X16) Array Organization
1 Block = 64 Pages
(64K + 2k) Word
64K Pages
(=1,024 Blocks)
1K Words
32 Words
1 Page = (1K + 32)Words
1 Block = (1K + 32)Word x 64 Pages
= (64K + 2K) Words
1 Device = (1K+32)Word x 64Pages x 1024 Blocks
= 1056 Mbits
16 bit
Page Register
1K Words
I/O 0 ~ I/O 15
32 Words
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A8 A9 A10 *L *L *L *L
3rd Cycle A11 A12 A13 A14 A15 A16 A17
4th Cycle A19 A20 A21 A22 A23 A24 A25
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
I/O 7
A7
*L
A18
A26
I/O8 ~ 15
*L
*L
*L
*L
Column Address
Column Address
Row Address
Row Address
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K9D1G08V0M equivalent, schematic
K9F1G08Q0M K9F1G16Q0M
K9F1G08D0M K9F1G16D0M
K9F1G08U0M K9F1G16U0M
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Write 60h
Write Block Address
Start
Write 00h
Write Address
Write D0h
Write 30h
Read Status Register
Read Data
I/O 6 = 1 ?
or R/B = 1 ?
No
* No
Erase Error
Yes
I/O 0 = 0 ?
Yes
Erase Completed
ECC Generation
No
Reclaim the Error
Verify ECC
Yes
Page Read Completed
* : If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
{1st
(n-1)th
nth
Block A
an error occurs.
(page)
1
Buffer memory of the controller.
{1st
(n-1)th
nth
(page)
Block B
2
* Step1
When an error happens in the nth page of the Block ’A’during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program to Block ’A’by creating an ’invalid Block’table or other appropriate scheme.
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