DataSheet8.cn


PDF ( 数据手册 , 数据表 ) K7A401800B

零件编号 K7A401800B
描述 128Kx36/x32 & 256Kx18 Synchronous SRAM
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


1 Page

No Preview Available !

K7A401800B 数据手册, 描述, 功能
K6X8016C3B Family
Document Title
512Kx16 bit Low Power Full CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 Initial draft
0.1 Revised
- Deleted 44-TSOP2-400R package type.
- Added Commercial product.
0.11
Revised
- Errata correction : corrected commercial product family name from
K6X8016C3B-F to K6X8016C3B-B in PRODUCT FAMILY.
1.0 Finalized
- Changed ICC from 12mA to 6mA
- Changed ICC1 from 12mA to 7mA
- Changed ICC2 from 60mA to 35mA
- Changed ISB from 3mA to 0.4mA
- Changed ISB1(Commercial) from 40µA to 25µA
- Changed ISB1(industrial) from 40µA to 25µA
- Changed ISB1(Automotive) from 50µA to 40µA
- Changed IDR(Commercial) from 30µA to 15µA
- Changed IDR(industrial) from 30µA to 15µA
- Changed IDR(Automotive) from 40µA to 30µA
Draft Date
October 31, 2002
Remark
Preliminary
December 11, 2002 Preliminary
March 26, 2003
Preliminary
September 16, 2003 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 1.0
September 2003







K7A401800B pdf, 数据表
K6X8016C3B Family
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
Address
CS
UB, LB
WE
Data in
tAS(3)
tWC
tCW(2)
tAW
tBW
tWP(1)
tWR(4)
tDW tDH
Data Valid
CMOS SRAM
Data out
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC
4.5V
tSDR
2.2V
VDR
CS
GND
Data Retention Mode
CSVCC - 0.2V
tRDR
8 Revision 1.0
September 2003














页数 9 页
下载[ K7A401800B.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
K7A401800B128Kx36/x32 & 256Kx18 Synchronous SRAMSamsung semiconductor
Samsung semiconductor
K7A401800B-QC128Kx36/x32 & 256Kx18 Synchronous SRAMSamsung semiconductor
Samsung semiconductor

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap