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PDF ( 数据手册 , 数据表 ) K6F2008V2E-YF70

零件编号 K6F2008V2E-YF70
描述 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
制造商 Samsung semiconductor
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K6F2008V2E-YF70 数据手册, 描述, 功能
K6F2008V2E Family
CMOS SRAM
Document Title
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0 Initial draft
Draft Date
July 19 , 2001
Remark
Preliminary
1.0 Finalize
September 27, 2001 Final
1.1 Revised
May 13, 2003
- Added Lead Free(LF) product for 32-TSOP1-0813.4F(LF) package.
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 1.1
May 2003







K6F2008V2E-YF70 pdf, 数据表
K6F2008V2E Family
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
Address
CS1
CS2
WE
tAS(3)
tWC
tAW
tCW(2)
tWP(1)
Data in
CMOS SRAM
tWR(4)
tDW tDH
Data Valid
Data out
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
3.0V
tSDR
2.2V
VDR
CS1
GND
CS2 controlled
VCC
3.0V
CS2
tSDR
VDR
0.4V
GND
Data Retention Mode
CS1VCC - 0.2V
Data Retention Mode
CS20.2V
tRDR
tRDR
8 Revision 1.1
May 2003














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