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PDF ( 数据手册 , 数据表 ) S524LB0XB1

零件编号 S524LB0XB1
描述 32K/64K-bit Serial EEPROM
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


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S524LB0XB1 数据手册, 描述, 功能
S524LB0X91/B0XB1
32K/64K-bit
Serial EEPROM
Data Sheet
OVERVIEW
The S524LB0D91/B0DB1 serial EEPROM has a 32/64 Kbits (4,096/8,192 bytes) capacity, supporting the
standard I2C™-bus serial interface. It is fabricated using Samsungs’ most advanced CMOS technology. One of
its major features is a hardware-based write protection circuit for the entire memory area. Hardware-based write
protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to
32 bytes of data into the EEPROM in a single write operation. Another significant feature of the
S524LB0D91/B0DB1 is its support for fast mode and standard mode.
FEATURES
I2C-Bus Interface
Two-wire serial interface
Automatic word address increment
EEPROM
32/64 Kbits (4,096/8,192 bytes) storage area
32-byte page buffer
Typical 3-millisecond write cycle time with auto-
erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
Operating Characteristics
Operating voltage: 2.0 V to 5.5 V
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 500 µA at 5.5 V
— Maximum stand-by current: < 2 µA at 2.0 V
Operating temperature range:
— – 25 °C to + 70 °C (Commercial)
— – 40 °C to + 85 °C (Industrial)
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 500 V (MM)
Packages
8-pin DIP and SOP
7-1







S524LB0XB1 pdf, 数据表
S524LB0D91/B0DB1 SERIAL EEPROM
DATA SHEET
BYTE WRITE OPERATION
A write operation requires 2-byte word addresses, the first (high) word address and the second (low) word
address. In a byte write operation, the master transmits the slave address, the first word address, the second
word address, and one data byte to the S524LB0D91/B0DB1 slave device (see Figure 7-10).
Start Slave Address
First Word Address Second Word Address
Data
Stop
AA A A
CC C C
KK K K
Figure 7-10. Byte Write Operation
Following a start condition, the master puts the device identifier (4 bits), the device address (3 bits), and an R/W
bit set to “0” onto the bus. Upon the receipt of the slave address, the S524LB0D91/B0DB1 responds with an ACK.
And the master transmits the first word address, the second word address, and one byte data to be written into
the addressed memory location.
The master terminates the transfer by generating a stop condition, at which time the S524LB0D91/B0DB1 begins
the internal write cycle. While the internal write cycle is in progress, all S524LB0D91/B0DB1 inputs are disabled
and the S524LB0D91/B0DB1 does not respond to any additional request from the master.
7-8







S524LB0XB1 equivalent, schematic
S524LB0D91/B0DB1 SERIAL EEPROM
DATA SHEET
SCL
SDA In
tSU:STA
SDA Out
tF tHIGH
tLOW
tR
tHD:STA
tHD:DAT
tSU:DAT
tAA
tSU:STO
tBUF
Figure 7-16. Timing Diagram for Bus Operations
SCL
SDA
8th Bit
WORDn
ACK
Stop
Condition
tWR
Start
Condition
Figure 7-17. Write Cycle Timing Diagram
7-16










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