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零件编号 | S524C20D11 | ||
描述 | 1K/2K/4K/8K-bit Serial EEPROM | ||
制造商 | Samsung semiconductor | ||
LOGO | |||
1 Page
S524C20D11/20D21/80D41/80D81
1K/2K/4K/8K-bit
Serial EEPROM
Data Sheet
OVERVIEW
The S524C20D11/20D21/80D41/80D81 serial EEPROM has a 1,024/2,048/4,096/8,192-bit (128/256/512/1,024-
byte) capacity, supporting the standard I2C™-bus serial interface. It is fabricated using Samsungs’ most
advanced CMOS technology. One of its major feature is a hardware-based write protection circuit for the entire
memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-
page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another
significant feature of the S524C20D11/20D21/80D41/80D81 is its support for fast mode and standard mode.
FEATURES
I2C-Bus Interface
• Two-wire serial interface
• Automatic word address increment
EEPROM
• 1K/2K/4K/8K-bit (128/256/512/1,024-byte)
storage area
• 16-byte page buffer
• Typical 3.5 ms write cycle time with
auto-erase function
• Hardware-based write protection for the entire
EEPROM (using the WP pin)
• EEPROM programming voltage generated
on chip
• 1,000,000 erase/write cycles
• 100 years data retention
Operating Characteristics
• Operating voltage
— 2.5 V to 5.5 V (write)
— 2.2 V to 5.5 V (read)
• Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 µA at 5.5 V
— Maximum stand-by current: < 5 µA at 3.3 V
• Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
• Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
• Electrostatic discharge (ESD)
— 3,000 V (HBM)
— 300 V (MM)
Packages
• 8-pin DIP, SOP, and TSSOP
3-1
S524C20D11/20D21/80D41/80D81 SERIAL EEPROM
DATA SHEET
BYTE WRITE OPERATION
In a complete byte write operation, the master transmits the slave address, word address, and one data byte to
the S524C20D11/20D21/80D41/80D81 slave device (see Figure 3-9).
Start Slave Address
Word Address
Data
Stop
AAA
CCC
KKK
Figure 3-9. Byte Write Operation
Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and an
R/W bit set to “0” onto the bus. Then the addressed S524C20D11/20D21/80D41/80D81 generates an ACK and
waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is
written into the word address pointer of the S524C20D11/20D21/80D41/80D81.
When the S524C20D11/20D21/80D41/80D81 receives the word address, it responds by issuing an ACK and then
waits for the next 8-bit data. When it receives the data byte, the S524C20D11/20D21/80D41/80D81 again
responds with an ACK. The master terminates the transfer by generating a Stop condition, at which time the
S524C20D11/20D21/80D41/80D81 begins the internal write cycle.
While the internal write cycle is in progress, all S524C20D11/20D21/80D41/80D81 inputs are disabled and the
S524C20D11/20D21/80D41/80D81 does not respond to additional requests from the master.
3-8
S524C20D11/20D21/80D41/80D81 SERIAL EEPROM
DATA SHEET
SCL
SDA In
tSU:STA
SDA Out
tF tHIGH
tLOW
tR
tHD:STA
tHD:DAT
tSU:DAT
tAA
tSU:STO
tBUF
Figure 3-16. Timing Diagram for Bus Operations
SCL
SDA
8th Bit
WORDn
ACK
Stop
Condition
tWR
Start
Condition
Figure 3-17. Write Cycle Timing Diagram
3-16
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页数 | 20 页 | ||
下载 | [ S524C20D11.PDF 数据手册 ] |
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