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零件编号 | S524A40X40 | ||
描述 | 1K/2K/4K-bit Serial EEPROM for Low Power with software write protect | ||
制造商 | Samsung semiconductor | ||
LOGO | |||
1 Page
S524A40X10/40X20/40X40
1K/2K/4K-bit
Serial EEPROM for Low Power
with software write protect
Data Sheet
OVERVIEW
The S524A40X10/40X20/40X40 serial EEPROM has a 1,024/2,048/4,096-bit (128/256/512-byte) capacity,
supporting the standard I2C™-bus serial interface. It is fabricated using Samsungs’ most advanced CMOS
technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). Important features
are a hardware-based write protection circuit for the entire memory area and software-based write protection logic
for the lower 128 bytes. Hardware-based write protection is controlled by the state of the write-protect (WP) pin.
The software-based method is one-time programmable and permanent. Using one-page write mode, you can
load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the
S524A40X10/40X20/40X40 is its support for fast mode and standard mode.
FEATURES
I2C-Bus Interface
• Two-wire serial interface
• Automatic word address increment
EEPROM
• 1K/2K/4K-bit (128/256/512-byte) storage area
• 16-byte page buffer
• Typical 3 ms write cycle time with
auto-erase function
• Hardware-based write protection for the entire
EEPROM (using the WP pin)
• Software-based write protection for the lower
128-byte EEPROM
• EEPROM programming voltage generated
on chip
• 1,000,000 erase/write cycles
• 100 years data retention
Operating Characteristics
• Operating voltage
— 1.8 V to 5.5 V
• Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 µA at 5.5 V
— Maximum stand-by current: < 1 µA at 5.5 V
• Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
• Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
• Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 500 V (MM)
Packages
• 8-pin DIP, SOP, and TSSOP
2-1
S524A40X10/40X20/40X40 SERIAL EEPROM
DATA SHEET
BYTE WRITE OPERATION
In a complete byte write operation, the master transmits the slave address, word address, and one data byte to
the S524A40X10/40X20/40X40 slave device (see Figure 2-9).
Start Slave Address
Word Address
Data
Stop
AAA
CCC
KKK
Figure 2-9. Byte Write Operation
Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and an
R/W bit set to “0” onto the bus. Then the addressed S524A40X10/40X20/40X40 generates an ACK and waits for
the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into
the word address pointer of the S524A40X10/40X20/40X40.
When the S524A40X10/40X20/40X40 receives the word address, it responds by issuing an ACK and then waits
for the next 8-bit data. When it receives the data byte, the S524A40X10/40X20/40X40 again responds with an
ACK. The master terminates the transfer by generating a Stop condition, at which time the
S524A40X10/40X20/40X40 begins the internal write cycle.
While the internal write cycle is in progress, all S524A40X10/40X20/40X40 inputs are disabled and the
S524A40X10/40X20/40X40 does not respond to additional requests from the master.
2-8
S524A40X10/40X20/40X40 SERIAL EEPROM
DATA SHEET
Table 2-4. D.C. Electrical Characteristics (Continued)
(TA = – 25°C to + 70°C (C), – 40°C to + 85°C (I), VCC = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min Typ Max Unit
Input capacitance
CIN 25°C, 1MHz,
VCC = 5 V, VIN = 0 V,
A0, A1, A2, SCL and WP pin
–
– 10 pF
Input/output capacitance
CI/O 25°C, 1MHz,
VCC = 5 V, VI/O = 0 V,
SDA pin
– – 10
Table 2-5. A.C. Electrical Characteristics
(TA = – 25°C to + 70°C (C), – 40°C to + 85°C (I), VCC = 1.8 V to 5.5 V)
Parameter
Symbol Conditions
VCC = 1.8 to 5.5 V
(Standard Mode)
Min Max
External clock frequency
FCLK
–
0 100
Clock high time
tHIGH
–
4–
Clock low time
tLOW
–
4.7 –
Rising time
tR SDA, SCL
–
1
Falling time
tF SDA, SCL
–
0.3
Start condition hold time
tHD:STA
–
4–
Start condition setup time tSU:STA
–
4.7 –
Data input hold time
tHD:DAT
–
0–
Data input setup time
tSU:DAT
–
0.25 –
Stop condition setup time tSU:STO
–
4–
Bus free time
tBUF Before new
transmission
4.7
–
Data output valid from
clock low (note)
tAA
–
0.3 3.5
Noise spike width
tSP –
– 100
Write cycle time
tWR –
–5
VCC = 2.5 to 5.5 V
(Fast Mode)
Min Max
0 400
0.6 –
1.3 –
– 0.3
– 0.3
0.6 –
0.6 –
0–
0.1 –
0.6 –
1.3 –
– 0.9
– 50
–5
Unit
kHz
µs
ns
ms
NOTE: When acting as a transmitter, the S524A40X10/40X20/40X40 must provide an internal minimum delay time to
bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended
generation of a start or stop condition.
2-16
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页数 | 18 页 | ||
下载 | [ S524A40X40.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
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