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PDF ( 数据手册 , 数据表 ) S524A40X21

零件编号 S524A40X21
描述 1K/2K/4K/8K/16K-bit Serial EEPROM for Low Power
制造商 Samsung semiconductor
LOGO Samsung semiconductor LOGO 


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S524A40X21 数据手册, 描述, 功能
S524A40X11/40X21/
40X41/60X81/60X51
1K/2K/4K/8K/16K-bit
Serial EEPROM for Low Power
Data Sheet
OVERVIEW
The S524A40X11/40X21/40X41/60X81/60X51 serial EEPROM has a 1,024/2,048/4,096/8,192/16,384-bit
capacity, supporting the standard I2C™-bus serial interface. It is fabricated using Samsung’s most advanced
CMOS technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its
major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write
protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to
16 bytes of data into the EEPROM in a single write operation. Another significant feature of the
S524A40X11/40X21/40X41/60X81/60X51 is its support for fast mode and standard mode.
FEATURES
I2C-Bus Interface
Two-wire serial interface
Automatic word address increment
EEPROM
1K/2K/4K/8K/16K-bit
(128/256/512/1,024/2,048-byte) storage area
16-byte page buffer
Typical 3 ms write cycle time with
auto-erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
Operating Characteristics
Operating voltage
— 1.8 V to 5.5 V
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 µA at 5.5 V
— Maximum stand-by current: < 1 µA at 5.5 V
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 500 V (MM)
Packages
8-pin DIP, SOP, and TSSOP
1-1







S524A40X21 pdf, 数据表
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
DATA SHEET
BYTE WRITE OPERATION
In a complete byte write operation, the master transmits the slave address, word address, and one data byte to
the S524A40X11/40X21/40X41/60X81/60X51 slave device (see Figure 1-9).
Start Slave Address
Word Address
Data
Stop
AAA
CCC
KKK
Figure 1-9. Byte Write Operation
Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and an
R/W bit set to “0” onto the bus. Then the addressed S524A40X11/40X21/40X41/60X81/60X51 generates an ACK
and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address
is written into the word address pointer of the S524A40X11/40X21/40X41/60X81/60X51.
When the S524A40X11/40X21/40X41/60X81/60X51 receives the word address, it responds by issuing an ACK
and then waits for the next 8-bit data. When it receives the data byte, the
S524A40X11/40X21/40X41/60X81/60X51 again responds with an ACK. The master terminates the transfer by
generating a Stop condition, at which time the S524A40X11/40X21/40X41/60X81/60X51 begins the internal write
cycle.
While the internal write cycle is in progress, all S524A40X11/40X21/40X41/60X81/60X51 inputs are disabled and
the S524A40X11/40X21/40X41/60X81/60X51 does not respond to additional requests from the master.
1-8







S524A40X21 equivalent, schematic
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
DATA SHEET
SCL
SDA In
tSU:STA
SDA Out
tF tHIGH
tLOW
tR
tHD:STA
tHD:DAT
tSU:DAT
tAA
tSU:STO
tBUF
Figure 1-15. Timing Diagram for Bus Operations
SCL
SDA
8th Bit
WORDn
ACK
Stop
Condition
tWR
Start
Condition
Figure 1-16. Write Cycle Timing Diagram
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