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PDF ( 数据手册 , 数据表 ) IP1202

零件编号 IP1202
描述 Dual Output Full Function 2 Phase Synchronous Buck Power Block Integrated Power Semiconductors/ PWM Control & Passives
制造商 International Rectifier
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IP1202 数据手册, 描述, 功能
PD-94593C
iP1202
Features
• 5.5V to 13.2V input voltage
• 0.8V to 5V output voltage
• 2 Phase Synchronous Buck Power Block
• 180° out of phase operation
• Single or Dual output capability
• Dual 15A maximum load capability
• Single 2 phase 30A maximum load capability
• 200-400kHz per channel nominal switching frequency
• Over Current Hiccup or Over Current Latch
• External Synchronization Capable
• Overvoltage protection
• Individual soft start per outputs
• Over Temperature protection
• Internal features minimize layout sensitivity *
• Ease of layout
• Very small outline 15.5mm x 9.25mm x 2.6mm
Description
Dual Output Full Function 2 Phase
Synchronous Buck Power Block
Integrated Power Semiconductors,
PWM Control & Passives
iP1202 Power Block
The iP1202 is a fully optimized solution for medium current synchronous buck applications requiring up to 15A
or 30A. The iP1202 is optimized for 2 phase single output applications up to 30A or dual output, each up to
15A with interleaved input. It includes full function PWM control, with optimized power semiconductor chip-sets
and associated passives, achieving high power density. Very few external components are required to create
a complete synchronous buck power supply.
iPOWIR technology offers designers an innovative space-saving solution for applications requiring high power
densities. iPOWIR technology eases design for applications where component integration offers benefits in
performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat
transfer and component selection.
iP1202 Configurations
Channel 1
V IN
V OUT
V IN
V OUT
Channel 2
V OUT
Single Output
Dual Output
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques
should be applied for the design of the power supply board. The iPOWIR block will function normally, but not optimally without any additional input decoupling
capacitors. Input decoupling capacitors should be added at Vin pin for stable and reliable long term operation. See layout guidelines in datasheet for more
detailed information.
www.irf.com
10/28/04
1







IP1202 pdf, 数据表
iP1202
Output2
(Fig. 2)
(Fig. 4)
(Fig. 5)
(Fig. 6)
(Fig. 7)
Maximum power loss =6.4W /2 = 3.2W
Normalized power loss for input voltage 0.93
Normalized power loss for output voltage 1.075
Normalized power loss for frequency 1.0
Normalized power loss for inductor value 0.98
Adjusted Power Loss = 3.2W x 0.93 x 1.075 x 1.0 x 0.98 3.13W
Total device power loss = 3.7W + 3.13W 6.8W
Example 2) Adjusting for SOA Temperature:
Assuming TCASE = 110°C & TPCB = 90°C for both outputs
Output1 (Fig. 4) Normalized SOA Temperature for input voltage -2.3°C
(Fig. 5) Normalized SOA Temperature for output voltage -0.6°C
(Fig. 6) Normalized SOA Temperature for frequency 0°C
(Fig. 7) Normalized SOA Temperature for inductor value ≈−0.7°C
TX axis intercept temp adjustment = -2.3°C - 0.6°C + 1.9°C - 0.7°C -3.6°C
The following example shows how the SOA current is adjusted for a TX change of -3.6°C and output 1 is in SOA
Cas e Te m pe rature (ž8Ã
0
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
10 20 30 40 50 60 70 80 90 100 110 120
A djusted SOA Current
Unadjusted SOA Current
S afe
Operating
Area
TX
V IN = 12V
V OUT 1 = V OUT 2 = 1.5V
IOUT = 15A
f SW = 300kHz
L = 1.8uH
10 20 30 40 50 60 70 80 90 100 110 120
PCB Temperature (ºC)
Output2
(Fig. 4)
(Fig. 5)
(Fig. 6)
(Fig. 7)
Normalized SOA Temperature for input voltage -2.3°C
Normalized SOA Temperature for output voltage 3.9°C
Normalized SOA Temperature for frequency 0°C
Normalized SOA Temperature for inductor value ≈ −0.7°C
TX axis intercept temp adjustment = -2.3°C + 3.9°C - 0°C - 0.7°C 0.9°C
The following example shows how the SOA current is adjusted for a TX change of 0.9°C and output 2 is in SOA.
Cas e Tem perature (ž8Ã
16 0
10 20 30 40 50 60 70
80 90 100 110 120
15
14
13 Unadjusted SOA Current
12 A djusted SOA Current
11
10 Safe
9 Operating
8 Area
7
6
TX
5
4
3
2
V IN = 12V
V OUT1 = V OUT2 = 1.5V
IOUT = 15A
f SW = 300kHz
1 L = 1.8uH
0
0 10 20 30 40 50 60 70 80 90 100 110 120
PCB Temperature (ºC)
8
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IP1202 equivalent, schematic
iP1202
iP1202 Design Procedure
Only a few external components are required to com-
plete a dual output synchronous buck power supply
using iP1202. The following procedure will guide the
designer through the design and selection process
of these external components.
A typical application for iP1202 will be:
VIN = 12V, VOUT1 = 1.5V, IOUT1 = 15A, VOUT2 = 2.5V, IOUT2
= 10A, fsw = 300kHz, Vp-p1 = Vp-p2 = 50mV
Setting the Output Voltage
The output voltage of the iP1202 is set by the 0.8V
reference Vref and external voltage dividers.
Vout1
R9
FB1
iP1202
R7
R13
FB1S
C26
(Optional)
R14
Fig. 17: Typical scheme for output voltage setting
For Type II compensation,
VOUT1 is set according to equation (1):
VOUT1 = Vref x (1 + R9 /R7 ) (see Fig. 17)
(1)
Setting R7 to 1K, VOUT1 to 1.5V and Vref to 0.8V, will
result in R9= 875 ohms (select 887 ohms). Final val-
ues can be selected according to the desired accu-
racy of the output.
To set the output voltage for Type III compensation,
refer to equation (25) in Type III compensation sec-
tion.
If the 0.8V reference is used to set the voltage for the
second output VOUT2, VP-ref pin must be shorted to
Vref pin and in a similar way, voltage divider resistors
are selected for the second output VOUT2. The second
output can also be set by applying an external refer-
16
ence source to VP-ref. In this case, to ensure proper
start-up, power to VP-ref and iP1202 must be ap-
plied simultaneuosly.
Setting the Overvoltage Trip
Both outputs of the iP1202 will shut down if either
one of the outputs experiences a voltage in the range
of 115% of VOUT. The overvoltage sense pins FB1s
and FB2s are connected to the output through volt-
age dividers, R13 and R14 (Fig. 17), and the trip
setpoints are programmed according to equation (1).
Separate overvoltage sense pins FB1s and FB2s are
provided to protect the power supply output if for some
reason the main feedback loop is lost (for instance,
loss of feedback resistors). An optional 100pF ca-
pacitor (C26) is used for delay and filtering purposes.
If this redundancy is not required and if Type II con-
trol loop compensation scheme is utilized, FB1s and
FB2s pins can be connected to FB1 and FB2 pins
respectively.
In parallel configuration, FB2s should be connected
to FB1s
Setting the Soft-Start Capacitor
The soft start capacitor Css is selected according to
equation (2):
tss = 40 x Css
(2)
where,
tss is the output voltage ramp time in milliseconds,
and Css is the soft start capacitor in µF.
A 0.1µF capacitor will provide an output voltage ramp-
up time of about 4ms.
Input Capacitor Selection
The switching currents impose RMS current require-
ments on the input capacitors. The expression in
equation (3) allows the selection of the input capaci-
tors for duty cycles less than 0.5:
( )I RMS =
I
2
1
D1
(1
D1
)
+
I
2
2
D2
(1
D2
)
2I1I
2
D1
D2
(3)
where, I1 and I2 are the load currents for outputs 1
and 2 respectively and D1 and D2 are the duty cycles
for channel 1 and channel 2 respectively.
For output1 of the above example D= 0.13 and,
For output2 of the above example D = 0.21 and,
For the above example, using equation (3) the ca-
pacitor rms current yields 5.8A.
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