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PDF ( 数据手册 , 数据表 ) 7013

零件编号 7013
描述 CMOS TIA IS-54 Baseband Receive Port
制造商 Analog Devices
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7013 数据手册, 描述, 功能
a
CMOS
TIA IS-54 Baseband Receive Port
AD7013
FEATURES
Single +5 V Supply
Receive Channel
Differential or Single-Ended Analog Inputs
Auxiliary Set of Analog I & Q Inputs
Two Sigma-Delta A/D Converters
Choice of Two Digital FIR Filters
Root-Raised-Cosine Rx Filters, α = 0.35
Brick Wall FIR Rx Filters
On-Chip or User Rx Offset Calibration
ADC Sampling Vernier
Three Auxiliary DACs
On-Chip Voltage Reference
Low Active Power Dissipation, Typical 45 mW
Low Sleep Mode Power Dissipation, <50 µW
28-Pin SSOP
APPLICATIONS
American TIA Digital Cellular Telephony
American Analog Cellular Telephony
Digital Baseband Receivers
GENERAL DESCRIPTION
The AD7013 is a complete low power, CMOS, TIA IS-54 base-
band receive port with single +5 V power supply. The part is
designed to perform the baseband conversion of I and Q
waveforms in accordance with the American (TIA IS-54)
Digital Cellular Telephone system.
The receive path consists of two high performance sigma-delta
ADCs, each followed by a FIR digital filter. A primary and
auxiliary set of IQ differential analog inputs are provided,
where either can be selected as inputs to the sigma-delta
ADCs. Also, a choice of two frequency responses are available
for the receive FIR filters; a Root-Raised-Cosine filter for
digital mode or a brick wall response for analog mode.
Differential analog inputs are provided for both I and Q
channels. On-chip calibration logic is also provided to remove
either on-chip offsets or remove system offsets. A 16-bit serial
interface is provided, interfacing easily to most DSPs. The
receive path also provides a means to vary the sampling
instant, giving a resolution to 1/32 of a symbol interval.
The auxiliary section provides two 8-bit DACs and one 10-bit
DAC for functions such as automatic gain control (AGC),
automatic frequency control (AFC) and power amplifier
control.
As it is a necessity for all digital mobile systems to use the
lowest possible power, the device has receive and auxiliary
power down options. The AD7013 is housed in a space
efficient 28-pin SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
DxCLK
DATA IN
FRAME IN
MODE1
FRAME OUT
Rx CLK
Rx DATA
Rx FRAME
MCLK
DGND VDD
AUX DAC1 AUX DAC2 AUX DAC3
FS ADJUST VAA AGND
SERIAL
INTERFACE
RECEIVE
CHANNEL
SERIAL
INTERFACE
10-BIT
AUX DAC
8-BIT
AUX DAC
8-BIT
AUX DAC
FULL-SCALE
ADJUST
LATCH
LATCH
OFFSET
ADJUST
ANALOG MODE
FIR DIGITAL FILTER
ROOT RAISED COSINE
FIR DIGITAL FILTER
LATCH
1.23V
REFERENCE
AD7013
∆Σ
MODULATOR
SWITCHED
CAP FILTER
MUX
OFFSET
ADJUST
ANALOG MODE
FIR DIGITAL FILTER
ROOT RAISED COSINE
FIR DIGITAL FILTER
∆Σ
MODULATOR
SWITCHED
CAP FILTER
MUX
AGND
AGND
BYPASS
IRx
IRx
AUX IRx
AUX IRx
QRx
QRx
AUX QRx
AUX QRx
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703







7013 pdf, 数据表
AD7013
RECEIVE SECTION TIMING (VAA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND =0 V, fMCLK = 6.2208 MHz;
TA = TMIN to TMAX, unless otherwise noted)
Parameter
t26
t27
t28
t29
t30
t31
t32
t33
t34
t35
t36
t37
Limit at TA =
–40°C to +85°C
10240t1
6144t1
30
85
4t1
2t1–20
2t1–20
–10
+10
64t1
4t1
–10
+10
12t1
128t1
2t1 + 20
2t1 + 20
Units
ns max
ns max
ns min
ns max
ns
ns min
ns min
ns min
ns max
ns
ns
ns min
ns max
ns min
ns max
ns max
ns max
Description
Power up Receive to RxCLK
CR13 = 0; Rx Offset Autocalibration On
CR13 = 1; Rx Offset autocalibration Off
Propagation Delay from MCLK Rising Edge to RxCLK Rising Edge
RxCLK Cycle Time; CR10 = 0; 2x Sampling of the Symbol Rate
RxCLK High Pulse Width; CR10 = 0
RxCLK Low Pulse Width; CR10 = 0
RxCLK Rising Edge to RxFRAME Rising Edge
RxCLK to RxFRAME Propagation Delay
RxFRAME Cycle Time; CR10 = 0
RxFRAME High Pulse Width; CR10 = 0
Propagation Delay from RxCLK Rising Edge to RxDATA Valid
DxCLK Rising Edge to Last Falling Edge of RxCLK
3-State to Receive Channel Valid
Receive Channel to 3-State Relinquish Time
1t37 is derived from the measured time taken by the receive channel outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured
number is then extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the
Timing Characteristics is the true relinquish time of the part and as such is independent of external loading capacitance.
MCLK (I)
DxCLK (O)
CR14
RxCLK (O)
RxFRAME (O)
RxDATA (O)
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to One
t26
t27
t31 t32
t34
1MSB
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to Zero
t28
1LSB
t29
t30
t33
1 Q MSB
t35
Q LSB
0
15-BIT I WORD
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
I/Q FLAG BIT
15-BIT I WORD
I/Q FLAG BIT
Figure 4. Receive Serial Interface Timing with 2 × Sampling of the Symbol Rate (CR10 = 0)
DxCLK (O)
CR18
RxCLK (O)
RxFRAME (O)
RxDATA (O)
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to Zero
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to One
t36
3- STATE
ACTIVE
t37
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
3- STATE
Figure 5. Receive Serial Interface 3-State Timing
–8– REV. A







7013 equivalent, schematic
AD7013
Low Sampling Rate (CR10 = 0)
The timing diagram for the receive interface is shown in Figure 4.
The output word rate per channel is equal to 48.6 kHz (MCLK/
128) which corresponds to two times the symbol rate. The low
sampling rate operates in a similar manner to that described for the
high sampling rate.
AUXILIARY DACs
One 10-bit auxiliary DAC and two 8-bit auxiliary DACs are
provided for extra control functions such as automatic gain control,
automatic frequency control and power control. Figure 22
illustrates a simplified block diagram of the auxiliary DACs. The
AUX DACs consist of high impedance current sources, designed to
operate at very low currents while maintaining their DC accuracy.
The DACs are designed using a current segmented architecture.
The bit currents corresponding to each digital input are either
routed to the analog output (bit = 1) or to AGND (bit = 0).
Each of the auxiliary DACs has independent low power sleep
modes. The command register has three control bits CR17, CR16
and CR15 which control AUX DAC1, AUX DAC2 and AUX
DAC3 respectively. A logic 0 represents low power sleep mode and
a logic 1 represents normal operation.
The full-scale currents of the auxiliary DACs are controlled by a
single external resistor, RSET, connected between the FS ADJUST
pin and AGND. The relationship between full-scale current and
RSET is given as follows:
10-Bit AUX DAC
AUX DACFULL SCALE (mA) = 7992 × VREF (V)/ RSET ()
8-Bit AUX DACs
AUX DACFULL SCALE (mA) = 3984 × VREF (V)/ RSET ()
By using smaller values of RSET, thereby increasing AUX DAC full-
scale current, improved INL and DNL performance is possible as
shown in Table V.
Table V. AUX DAC1 INL and DNL as a Function of RSET
RSET
18 k
9 k
4.5 k
Worst Case
INL (LSBs)
–1.45
+1.22
+1.18
Worst Case
DNL (LSBs)
+1.83
+1.59
+1.38
Digital Interface
Communication with the Command register, auxiliary DACs, ADC
offset registers and ADC vernier is accomplished via the 3-pin serial
interface. Either one of two loading formats may be used to write
to any of the AD7013’s internal registers. The first format consists
of a single 16-bit serial word to write to any internal register (Table
III). The second format consists of five 16-bit serial words, where
only the last 6 bits in each 16-bit word are used to load five 2-bit
data nibbles. The load sequence for this format is given is Table IV.
The second format is only enable when the Register Address 3 is
used as the destination register as shown in Table I.
PCB Layout Considerations
The use of an analog ground plane is recommended, where the
ground plane extends around the analog circuitry. Both AGND and
DGND should be externally tied together and connected to the
analog ground plane.
Good power supply decoupling is very important for best ADC
performance. A 0.1 µF ceramic decoupling capacitor should be
connected between VAA and the ground plane. The physical place-
ment of the capacitor (surface mount if possible) is important and
should be placed as close to the pin of the device as is physically
possible. This is also applied to the VDD pin. Poor power supply
decoupling can lead to a degradation in ADC offsets and SNR.
The Bypass pin should be decoupled to the ground plane using a
10 nF capacitor. Large capacitor values are not recommended as
this can cause the reference not to reach its final value, on power
up, before ADC autocalibration has commenced.
Capacitive loading of digital outputs should be minimized as much
as possible if power dissipation is a critical factor. The charging
and discharging of external load capacitances can be a significant
contribution to power dissipation, especially when the AD7013 is in
a low power sleep mode as the DxCLK remains active.
VREF
(1.23V)
FULL–SCALE
ADJUST
CONTROL
AD7013
10-BIT
AUX DAC1
8-BIT
AUX DAC2
8-BIT
AUX DAC3
RSET 18k
4.5k
9k
AGND
AGND
AGND
Figure 22. AUX DACs
9k
AGND
AUX DAC1,
AUX DAC2
OR AUX DAC3
AD7013
FS ADJUST
BYPASS
10nF
RLOAD
RFB
+5V
1 TO 4 VOLTS
OP-295
RSET
18k
AUX DAC R LOAD
10-BIT
8-BIT
2.4k
11k
R FB
5.4k
4.9k
Figure 23. External Op Amp Circuitry to Extend Output
Voltage Range
–16–
REV. A










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