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PDF ( 数据手册 , 数据表 ) 7005

零件编号 7005
描述 ACT7005/7006 Single Package Solution Dual Transceiver/ Protocol/ Subsystem
制造商 Aeroflex Circuit Technology
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7005 数据手册, 描述, 功能
ACT7005/7006
Single Package Solution
Dual Transceiver, Protocol, Subsystem
Features
• Incorporates Transceivers, Protocol, and System Interface Components into a
Single Hybrid Package
• Functions as a Remote Terminal or Bus Controller
• Interfaces to µP as a Simple Peripheral Unit
• +5V Operation
CIRCUIT TECHNOLOGY
www.aeroflex.com
• Provides 2k by 16 of Double Buffered RAM Storage for Transmit and Receive
Subaddresses
• Pin Programmable for 8-bit or 16-bit Microprocessors
• Full Military (-55°C to +125°C) Temperature Range
General Description
The ACT7005/6 Series provides a complete one package interface between the MIL-STD-1553 bus and all
microprocessor systems. The hybrid provides all data buffers and control registers to function as a Bus
Controller or Remote Terminal. Control of the hybrid by the subsystem is through simple I/O port commands.
Internal hybrid logic removes all critical timing imposed on a typical subsystem, thereby simplifying the
implementation of this interface.
BUS "0"
DUAL
TX/RX
1553
PROTOCOL
BUS "1"
µP
INTERFACE
RAM
INTERRUPTS/
CONTROL
SIGNALS
S
U
B
S
Y
S
T
E
M
8/16
BIT
I/O
ACT7005 / ACT7006
Block Diagram
eroflex Circuit Technology – Data Bus Modules For The Future © SCD7005 REV B 8/2/01







7005 pdf, 数据表
SINGLE HYBRID
PROTOCOL SUBSYSTEM INTERFACE
KEY FEATURES
• Functional Superset of CT1800
• Downward compatible with existing designs base
of CT1800
• Incorporates Transceivers, Protocol and Interface
Hybrids into a single package
• Functions as a Remote Terminal or Bus Controller
GENERAL
The ACT7005/6 Series provides a complete
interface between the MIL-STD-1553 bus and any
micro-processor system. Functioning as a superset
of the CT1800 interface, the hybrid provides all data
buffers and control registers necessary to implement
RT and BC functions. Internal arbitration and data
transfer control circuitry eliminates subsystem
response requirements. All data written into or read
from this interface are double buffered on a message
basis. Only valid and complete receive messages
are transferred into the receive RAM.
The ACT7005/6 Series supports all 15 mode codes
and all types of data transfers allowed by
MIL-STD-1553B. All circuitry (excluding transceiver
drivers) are CMOS, which results in very low power
requirements.
Interfacing to the subsystem is simplified through
the use of tri-stated input/output buffers onto the
subsystem bus. Control signals basically consist of
four address lines, a device select input, read strobe,
write strobe, and several interrupts, the use of which
are optional. The Hybrid is accessed as a memory
mapped I/O port of a microprocessor system. Valid
transmission and reception of data are indicated to
the subsystem through the use of interrupts. This
frees up the system processor from actively
monitoring the port until a valid message is received.
OPERATION
The ACT7005/6 Series (Single Package Solution)
resides between a microprocessor interface and a
MIL-STD-1553 data bus. The addition of two
transformers and fault isolation resistors are the only
external components required to complete the
interface. Information on the bus is received or
transmitted through the transceiver (converted from
Manchester II to complimentary TTL signals and
visa versa) to the protocol section. The ACT7005/6
Series incorporates a single +5VDC only
transceiver.
The protocol section internally interfaces to the
transceivers. Control of the transceivers is provided
by the protocol section. This is determined by which
bus the command word was received on in the
remote terminal mode; or in the bus controller mode,
which bus was selected for transmission by the state
of a bit in the operation register. An autonomous
self-test can be performed either off-line or on-line
through the transceivers This self-test is controlled
by the operation register and will be discussed
thoroughly in the self-test section. The other test
function is that in addition to the protocol criteria that
is tested during every transmission; i.,e., proper sync
character, 16 data bits, Manchester II coded,
contiguous words, and odd parity, a bit per bit
comparison of the contents of the parallel data will
insure a higher degree of functionality of this section
of the hybrid.
Data received by the protocol section will be placed
in the receive FIFO buffer. Transmitted data will be
taken from the transmit FIFO buffer. Other than the
remote terminal address and parity, the discretes to
control the resetting of the terminal flag and
subsystem error bits, and a few discrete interrupts
and error signals, control over the protocol section
resides in the operation register of the subsystem
interface section.
The subsystem interface section has primary
control of the data that resides in the 2k of RAM. The
RAM is segregated into two 1k blocks of data, one
contains 30 blocks of transmit data messages and
the other one contains 30 blocks of receive data
messages. This is not absolute since the subsystem
has control of the A10 bit. Data entries to or from the
RAM are arbitrated by the control logic residing in
this function, and is buffered via FlFO’s on the input
from the protocol section and on the output to the
subsystem’s data bus. This guarantees that only
current and valid data blocks will reside in RAM. This
is true for remote terminal and bus controller
applications.
Seven dedicated registers are provided to ease the
interfacing with the subsystem. These will be
discussed in the Register Operation section of this
document. The register of primary concern to a
subsystem designer is the operation register. This
provides the means to accomplish data transfers to/
from the RAM, as well as control of remote terminal
or bus control modes of operation. All registers are
accessed via simple l/O commands, utilizing A0
through A3, Device Select, and Read or Write
strobes.
Receive Commands
When a valid receive command is received, it is first
loaded into the Command Word Register. The data
words associated with this command are received,
validated, and loaded one by one into the RCV FIFO
buffer. Once the entire message is received, and
only if the complete block of data is valid, will the
Aeroflex Circuit Technology
8 SCD7005 REV B 8/2/01 Plainview NY (516) 694-6700







7005 equivalent, schematic
Operation
Function
RESET
READ OUTPUT
DATA BUFFER
WRITE OUTPUT
DATA BUFFER
EXECUTE OP
RESET INPUT/OUTPUT BUFFERS
This command clears both the input and output FIFO buffers. The BUFF EF
flag will go low indicating the output buffer is empty.
READ OUTPUT FIFO
READS the data moved from the INTERNAL RAM in response to an
UNLOAD execute operation. The order of the data words corresponds to the
same order that they would be received on the 1553B bus. That is the first
data word read is the first data word following the COMMAND word. In the 8
bit mode the HIGH BYTE is read FIRST.
WRITE INPUT FIFO
WRITES the data that will be moved into the INTERNAL RAM in response to
a LOAD execute operation. The order of the data words corresponds to the
same order that they would be transmitted on the 1553B bus. That is the first
data word written is the first data word transmitted following the status word. In
8 bit mode the HIGH BYTE is written FIRST.
EXECUTES OPERATION SPECIFIED IN OPERATION REGISTER
1. I/O BIT HIGH
Data currently in INPUT FIFO BUFFER is loaded into the INTERNAL
RAM block specified by the T/R BIT and SUBADDRESS FIELD of the
OPERATION REGISTER. The INPUT BUFFER must have at least one
data word. The DONE interrupt is pulsed when the operation is
completed.
2. I/O BIT LOW
An entire block of data (32 words) specified by the T/R and the
SUBADDRESS field of the OPERATION REGISTER is unloaded from
the INTERNAL RAM into the OUTPUT FIFO BUFFER. The BUFF EF
Flag goes high when the first data word is moved into the OUTPUT
BUFFER. The DONE interrupt is pulsed when the complete message
has been moved.
EXECUTE OP
WITH RPT OPTION
EXECUTES OPERATION SPECIFIED IN OPERATION REGISTER WITH
REPEAT OPTION
1. I/O BIT HIGH
Data previously written into the INPUT BUFFER is loaded into a new
INTERNAL RAM block specified by the T/R and SUBADDRESS field of
the OPERATION REGISTER. This operation allows a block of data
loaded in the INPUT BUFFER to be repeatedly copied into multiple
subaddresses of the INTERNAL RAM without the subsystem having to
reload the data. The DONE interrupt is pulsed when the operation is
completed. The intent of the operation is to minimize the time required to
initialize the INTERNAL RAM.
2. I/O BIT LOW
Operation identical to EXECUTE OP. WITHOUT RPT option.
TRIGGER TRANSACTION TRANSACTION/TEST TRIGGER
TRIGGER TEST
This signal executes the desired Bus Controller Function or test of the
protocol section determined by the Operation Register.
Table 8 – Non-Register Operational Commands
Aeroflex Circuit Technology
16 SCD7005 REV B 8/2/01 Plainview NY (516) 694-6700










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